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| author | Tim Newsome <tim@sifive.com> | 2016-05-10 11:36:33 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2016-05-23 12:12:13 -0700 |
| commit | 6201d0ee2c20baf907079d9da7bae559a27f9382 (patch) | |
| tree | 1560cdf3feb5a0cb19345de0a72e0d1e9bb9d36e /riscv/mmu.cc | |
| parent | 9baa8a015cddc294d53d72ce57a8ca2f5c832c64 (diff) | |
| download | spike-6201d0ee2c20baf907079d9da7bae559a27f9382.zip spike-6201d0ee2c20baf907079d9da7bae559a27f9382.tar.gz spike-6201d0ee2c20baf907079d9da7bae559a27f9382.tar.bz2 | |
Ignore MPRV in Debug Mode.
Diffstat (limited to 'riscv/mmu.cc')
| -rw-r--r-- | riscv/mmu.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc index b88cade..e44c027 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -37,7 +37,7 @@ reg_t mmu_t::translate(reg_t addr, access_type type) reg_t mode = proc->state.prv; bool pum = false; if (type != FETCH) { - if (get_field(proc->state.mstatus, MSTATUS_MPRV)) + if (!proc->state.dcsr.cause && get_field(proc->state.mstatus, MSTATUS_MPRV)) mode = get_field(proc->state.mstatus, MSTATUS_MPP); pum = (mode == PRV_S && get_field(proc->state.mstatus, MSTATUS_PUM)); } |