diff options
author | Rupert Swarbrick <rswarbrick@gmail.com> | 2022-03-29 20:21:21 +0100 |
---|---|---|
committer | GitHub <noreply@github.com> | 2022-03-29 12:21:21 -0700 |
commit | cd2bc70a5d010161588f3cebcd2891514337e059 (patch) | |
tree | b2f666466fca5527f687bd7b86061d3ba7429cb8 /riscv/isa_parser.h | |
parent | 9a43019bfff59da7c42f1a95c636dd5ff5ec7f32 (diff) | |
download | spike-cd2bc70a5d010161588f3cebcd2891514337e059.zip spike-cd2bc70a5d010161588f3cebcd2891514337e059.tar.gz spike-cd2bc70a5d010161588f3cebcd2891514337e059.tar.bz2 |
Split isa_parser_t out of processor.* and into its own file (#955)
The main motivation for this is that we want to move the ISA parsing
logic to run before we even construct a simulator. That's probably a
bit nicer if we don't depend on the processor header.
It also means that we can stop depending on processor.h in disasm.cc
or spike_log_parser.cc (both through disasm.h), which feels a bit
cleaner: making sense of an instruction trace shouldn't really require
knowledge of the internal state of a processor.
Diffstat (limited to 'riscv/isa_parser.h')
-rw-r--r-- | riscv/isa_parser.h | 87 |
1 files changed, 87 insertions, 0 deletions
diff --git a/riscv/isa_parser.h b/riscv/isa_parser.h new file mode 100644 index 0000000..f32036c --- /dev/null +++ b/riscv/isa_parser.h @@ -0,0 +1,87 @@ +// See LICENSE for license details. +#ifndef _RISCV_ISA_PARSER_H +#define _RISCV_ISA_PARSER_H + +#include "decode.h" + +#include <vector> +#include <string> +#include <unordered_map> + +class extension_t; + +typedef enum { + // 65('A') ~ 90('Z') is reserved for standard isa in misa + EXT_ZFH, + EXT_ZFHMIN, + EXT_ZBA, + EXT_ZBB, + EXT_ZBC, + EXT_ZBS, + EXT_ZBKB, + EXT_ZBKC, + EXT_ZBKX, + EXT_ZKND, + EXT_ZKNE, + EXT_ZKNH, + EXT_ZKSED, + EXT_ZKSH, + EXT_ZKR, + EXT_ZMMUL, + EXT_ZBPBO, + EXT_ZPN, + EXT_ZPSFOPERAND, + EXT_SVNAPOT, + EXT_SVPBMT, + EXT_SVINVAL, + EXT_ZDINX, + EXT_ZFINX, + EXT_ZHINX, + EXT_ZHINXMIN, + EXT_ZICBOM, + EXT_ZICBOZ, + EXT_ZICNTR, + EXT_ZIHPM, + EXT_XZBP, + EXT_XZBS, + EXT_XZBE, + EXT_XZBF, + EXT_XZBC, + EXT_XZBM, + EXT_XZBR, + EXT_XZBT, +} isa_extension_t; + +typedef enum { + IMPL_MMU_SV32, + IMPL_MMU_SV39, + IMPL_MMU_SV48, + IMPL_MMU_SBARE, + IMPL_MMU, +} impl_extension_t; + +class isa_parser_t { +public: + isa_parser_t(const char* str, const char *priv); + ~isa_parser_t(){}; + unsigned get_max_xlen() const { return max_xlen; } + reg_t get_max_isa() const { return max_isa; } + std::string get_isa_string() const { return isa_string; } + bool extension_enabled(unsigned char ext) const { + if (ext >= 'A' && ext <= 'Z') + return (max_isa >> (ext - 'A')) & 1; + else + return extension_table[ext]; + } + const std::unordered_map<std::string, extension_t*> & + get_extensions() const { return extensions; } + +protected: + unsigned max_xlen; + reg_t max_isa; + std::vector<bool> extension_table; + std::string isa_string; + std::unordered_map<std::string, extension_t*> extensions; +}; + +#endif |