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| author | Andrew Waterman <andrew@sifive.com> | 2022-03-28 14:56:36 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-03-30 01:41:17 -0700 |
| commit | 1e159e462720f043b0c2ff9c0cd2541fed88f1a9 (patch) | |
| tree | 56f3251c9fec423e6e3cc9fa7856b8b400837888 /riscv/isa_parser.h | |
| parent | 3bbaab01762f0b5bac1fd816370c270ffe28fd6b (diff) | |
| download | spike-1e159e462720f043b0c2ff9c0cd2541fed88f1a9.zip spike-1e159e462720f043b0c2ff9c0cd2541fed88f1a9.tar.gz spike-1e159e462720f043b0c2ff9c0cd2541fed88f1a9.tar.bz2 | |
Implement Sv57 and Sv57x4 translation modes
Diffstat (limited to 'riscv/isa_parser.h')
| -rw-r--r-- | riscv/isa_parser.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/isa_parser.h b/riscv/isa_parser.h index f32036c..925dd3d 100644 --- a/riscv/isa_parser.h +++ b/riscv/isa_parser.h @@ -56,6 +56,7 @@ typedef enum { IMPL_MMU_SV32, IMPL_MMU_SV39, IMPL_MMU_SV48, + IMPL_MMU_SV57, IMPL_MMU_SBARE, IMPL_MMU, } impl_extension_t; |