diff options
| author | SeungRyeol Lee <zizztux.lee@lge.com> | 2015-10-28 15:59:10 +0900 |
|---|---|---|
| committer | SeungRyeol Lee <zizztux.lee@lge.com> | 2015-10-28 15:59:10 +0900 |
| commit | fe513f83ca9af7bb7601cfa4e19d3a9f71f669ed (patch) | |
| tree | 928708abec3143d8bc69d23448632caaec908ff9 /riscv/interactive.cc | |
| parent | 2ace4c98e65e72444a9017fa4f568fe9858addbe (diff) | |
| download | spike-fe513f83ca9af7bb7601cfa4e19d3a9f71f669ed.zip spike-fe513f83ca9af7bb7601cfa4e19d3a9f71f669ed.tar.gz spike-fe513f83ca9af7bb7601cfa4e19d3a9f71f669ed.tar.bz2 | |
Fix incorrect upper limit for loop on interactive int register display.
Diffstat (limited to 'riscv/interactive.cc')
| -rw-r--r-- | riscv/interactive.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/interactive.cc b/riscv/interactive.cc index 07b2801..8e22c02 100644 --- a/riscv/interactive.cc +++ b/riscv/interactive.cc @@ -216,7 +216,7 @@ void sim_t::interactive_reg(const std::string& cmd, const std::vector<std::strin // Show all the regs! processor_t *p = get_core(args[0]); - for (int r = 0; r < NFPR; ++r) { + for (int r = 0; r < NXPR; ++r) { fprintf(stderr, "%-4s: 0x%016" PRIx64 " ", xpr_name[r], p->state.XPR[r]); if ((r + 1) % 4 == 0) fprintf(stderr, "\n"); |