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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-06-06 03:13:52 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-06-18 08:54:10 -0700 |
| commit | 887dbf29497534ff5bf7906925f0f90aa060b778 (patch) | |
| tree | 30a65841a4b6f1ddcbc5b891e8c06c38aa9168ef /riscv/interactive.cc | |
| parent | 48fe0c484d50073bd5d12bdb7fef5b7ea257e006 (diff) | |
| download | spike-887dbf29497534ff5bf7906925f0f90aa060b778.zip spike-887dbf29497534ff5bf7906925f0f90aa060b778.tar.gz spike-887dbf29497534ff5bf7906925f0f90aa060b778.tar.bz2 | |
rvv: extend interactive debug
add command to show vector register in debug mode
Signed-off-by: Bruce Hoult <bruce@hoult.org>
Diffstat (limited to 'riscv/interactive.cc')
| -rw-r--r-- | riscv/interactive.cc | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/riscv/interactive.cc b/riscv/interactive.cc index c96c71a..40c53bf 100644 --- a/riscv/interactive.cc +++ b/riscv/interactive.cc @@ -66,6 +66,7 @@ void sim_t::interactive() funcs["run"] = &sim_t::interactive_run_noisy; funcs["r"] = funcs["run"]; funcs["rs"] = &sim_t::interactive_run_silent; + funcs["vreg"] = &sim_t::interactive_vreg; funcs["reg"] = &sim_t::interactive_reg; funcs["freg"] = &sim_t::interactive_freg; funcs["fregs"] = &sim_t::interactive_fregs; @@ -119,6 +120,7 @@ void sim_t::interactive_help(const std::string& cmd, const std::vector<std::stri "reg <core> [reg] # Display [reg] (all if omitted) in <core>\n" "fregs <core> <reg> # Display single precision <reg> in <core>\n" "fregd <core> <reg> # Display double precision <reg> in <core>\n" + "vreg <core> [reg] # Display vector [reg] (all if omitted) in <core>\n" "pc <core> # Show current PC in <core>\n" "mem <hex addr> # Show contents of physical memory\n" "str <hex addr> # Show NUL-terminated C string\n" @@ -218,6 +220,54 @@ freg_t sim_t::get_freg(const std::vector<std::string>& args) return p->get_state()->FPR[r]; } +void sim_t::interactive_vreg(const std::string& cmd, const std::vector<std::string>& args) +{ + int rstart = 0; + int rend = NVPR; + if (args.size() >= 2) { + rstart = strtol(args[1].c_str(), NULL, 0); + if (!(rstart >= 0 && rstart < NVPR)) { + rstart = 0; + } else { + rend = rstart + 1; + } + } + + // Show all the regs! + processor_t *p = get_core(args[0]); + const int vlen = (int)(p->VU.get_vlen()) >> 3; + const int elen = (int)(p->VU.get_elen()) >> 3; + const int num_elem = vlen/elen; + fprintf(stderr, "VLEN=%d bits; ELEN=%d bits\n", vlen << 3, elen << 3); + + for (int r = rstart; r < rend; ++r) { + fprintf(stderr, "%-4s: ", vr_name[r]); + for (int e = num_elem-1; e >= 0; --e){ + uint64_t val; + switch(elen){ + case 8: + val = P.VU.elt<uint64_t>(r, e); + fprintf(stderr, "[%d]: 0x%016" PRIx64 " ", e, val); + break; + case 4: + val = P.VU.elt<uint32_t>(r, e); + fprintf(stderr, "[%d]: 0x%08" PRIx32 " ", e, (uint32_t)val); + break; + case 2: + val = P.VU.elt<uint16_t>(r, e); + fprintf(stderr, "[%d]: 0x%08" PRIx16 " ", e, (uint16_t)val); + break; + case 1: + val = P.VU.elt<uint8_t>(r, e); + fprintf(stderr, "[%d]: 0x%08" PRIx8 " ", e, (uint8_t)val); + break; + } + } + fprintf(stderr, "\n"); + } +} + + void sim_t::interactive_reg(const std::string& cmd, const std::vector<std::string>& args) { if (args.size() == 1) { |