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| author | Wesley W. Terpstra <wesley@sifive.com> | 2017-03-21 16:40:01 -0700 |
|---|---|---|
| committer | Wesley W. Terpstra <wesley@sifive.com> | 2017-03-21 16:40:01 -0700 |
| commit | 4c80b12b1a96fee64bfbdd35d097d867599eee1e (patch) | |
| tree | 89e52f2a9850db98488b6078c353e6751705eaf6 /riscv/interactive.cc | |
| parent | f7a7557273b050ddc50dbff09c0c4bf8505e4ac7 (diff) | |
| download | spike-4c80b12b1a96fee64bfbdd35d097d867599eee1e.zip spike-4c80b12b1a96fee64bfbdd35d097d867599eee1e.tar.gz spike-4c80b12b1a96fee64bfbdd35d097d867599eee1e.tar.bz2 | |
riscv: remove dependency on num_cores
Diffstat (limited to 'riscv/interactive.cc')
| -rw-r--r-- | riscv/interactive.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/interactive.cc b/riscv/interactive.cc index 623c425..ee88375 100644 --- a/riscv/interactive.cc +++ b/riscv/interactive.cc @@ -24,7 +24,7 @@ processor_t *sim_t::get_core(const std::string& i) { char *ptr; unsigned long p = strtoul(i.c_str(), &ptr, 10); - if (*ptr || p >= num_cores()) + if (*ptr || p >= procs.size()) throw trap_interactive(); return get_core(p); } |