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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-07-31 20:38:50 +0800 |
|---|---|---|
| committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-08-10 22:34:27 +0800 |
| commit | 3bbce450315dece506aacf0662cbefa6f6948d4a (patch) | |
| tree | 21c458da3bb0d96adb4b1c8e7beca87e5a9e68fd /riscv/interactive.cc | |
| parent | 6b28c78b2cfdf562934fd1d65812cc8707f2cc41 (diff) | |
| download | spike-3bbce450315dece506aacf0662cbefa6f6948d4a.zip spike-3bbce450315dece506aacf0662cbefa6f6948d4a.tar.gz spike-3bbce450315dece506aacf0662cbefa6f6948d4a.tar.bz2 | |
Fix description for mem related interactive commands
Add missed description for untiln interactive commands
Diffstat (limited to 'riscv/interactive.cc')
| -rw-r--r-- | riscv/interactive.cc | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/riscv/interactive.cc b/riscv/interactive.cc index 4b29069..0b71507 100644 --- a/riscv/interactive.cc +++ b/riscv/interactive.cc @@ -211,15 +211,17 @@ void sim_t::interactive_help(const std::string& cmd, const std::vector<std::stri "fregd <core> <reg> # Display double precision <reg> in <core>\n" "vreg <core> [reg] # Display vector [reg] (all if omitted) in <core>\n" "pc <core> # Show current PC in <core>\n" - "mem <hex addr> # Show contents of physical memory\n" - "str <core> <hex addr> # Show NUL-terminated C string at <hex addr> in core <core>\n" + "mem [core] <hex addr> # Show contents of virtual memory <hex addr> in [core] (physical memory <hex addr> if omitted)\n" + "str [core] <hex addr> # Show NUL-terminated C string at virtual address <hex addr> in [core] (physical address <hex addr> if omitted)\n" "until reg <core> <reg> <val> # Stop when <reg> in <core> hits <val>\n" + "untiln reg <core> <reg> <val> # Run noisy and stop when <reg> in <core> hits <val>\n" "until pc <core> <val> # Stop when PC in <core> hits <val>\n" "untiln pc <core> <val> # Run noisy and stop when PC in <core> hits <val>\n" - "until mem <addr> <val> # Stop when memory <addr> becomes <val>\n" + "until mem [core] <addr> <val> # Stop when virtual memory <addr> in [core] (physical address <addr> if omitted) becomes <val>\n" + "untiln mem [core] <addr> <val> # Run noisy and stop when virtual memory <addr> in [core] (physical address <addr> if omitted) becomes <val>\n" "while reg <core> <reg> <val> # Run while <reg> in <core> is <val>\n" "while pc <core> <val> # Run while PC in <core> is <val>\n" - "while mem <addr> <val> # Run while memory <addr> is <val>\n" + "while mem [core] <addr> <val> # Run while virtual memory <addr> in [core] (physical memory <addr> if omitted) is <val>\n" "run [count] # Resume noisy execution (until CTRL+C, or [count] insns)\n" "r [count] Alias for run\n" "rs [count] # Resume silent execution (until CTRL+C, or [count] insns)\n" |