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| author | Tim Newsome <tim@sifive.com> | 2016-05-01 09:53:23 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2016-05-23 12:12:11 -0700 |
| commit | cb73c085a22b225576b5d5c22f74490f9e30a5a8 (patch) | |
| tree | dbdf77111d6ed2a5a334ec862e93b39ce50cb4a1 /riscv/insns | |
| parent | 784fea2bbec803944eb923196c77d38427b3f554 (diff) | |
| download | spike-cb73c085a22b225576b5d5c22f74490f9e30a5a8.zip spike-cb73c085a22b225576b5d5c22f74490f9e30a5a8.tar.gz spike-cb73c085a22b225576b5d5c22f74490f9e30a5a8.tar.bz2 | |
Properly save/restore dpc, mcause, mbadaddr.
Also clear dcsr.cause when leaving Debug Mode so future traps go where
they should.
Diffstat (limited to 'riscv/insns')
| -rw-r--r-- | riscv/insns/sret.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/riscv/insns/sret.h b/riscv/insns/sret.h index f5e89e4..dc2fee0 100644 --- a/riscv/insns/sret.h +++ b/riscv/insns/sret.h @@ -7,3 +7,6 @@ s = set_field(s, MSTATUS_SPIE, 0); s = set_field(s, MSTATUS_SPP, PRV_U); p->set_privilege(prev_prv); p->set_csr(CSR_MSTATUS, s); + +/* We're not in Debug Mode anymore. */ +STATE.dcsr.cause = 0; |