Implement RVC draft

22 files changed, 62 insertions, 8 deletions

diff --git a/riscv/insns/c_add.h b/riscv/insns/c_add.h
new file mode 100644
index 0000000..b2ba34f
--- /dev/null
+++ b/riscv/insns/c_add.h
@@ -0,0 +1,2 @@
+require_rvc;
+WRITE_RD(sext_xlen(RVC_RS1 + RVC_RS2));
diff --git a/riscv/insns/c_addi.h b/riscv/insns/c_addi.h
new file mode 100644
index 0000000..762f5c2
--- /dev/null
+++ b/riscv/insns/c_addi.h
@@ -0,0 +1,2 @@
+require_rvc;
+WRITE_RD(sext_xlen(RVC_RS2 + insn.rvc_imm()));
diff --git a/riscv/insns/c_addi4.h b/riscv/insns/c_addi4.h
new file mode 100644
index 0000000..90f3d81
--- /dev/null
+++ b/riscv/insns/c_addi4.h
@@ -0,0 +1,2 @@
+require_rvc;
+WRITE_RD(sext_xlen(RVC_RS2 + insn.rvc_lwsp_imm()));
diff --git a/riscv/insns/c_addiw.h b/riscv/insns/c_addiw.h
new file mode 100644
index 0000000..33f970c
--- /dev/null
+++ b/riscv/insns/c_addiw.h
@@ -0,0 +1,3 @@
+require_rvc;
+require_rv64;
+WRITE_RD(sext32(RVC_RS2 + insn.rvc_imm()));
diff --git a/riscv/insns/c_addw.h b/riscv/insns/c_addw.h
new file mode 100644
index 0000000..c474cda
--- /dev/null
+++ b/riscv/insns/c_addw.h
@@ -0,0 +1,3 @@
+require_rvc;
+require_rv64;
+WRITE_RD(sext32(RVC_RS1 + RVC_RS2));
diff --git a/riscv/insns/c_beqz.h b/riscv/insns/c_beqz.h
new file mode 100644
index 0000000..8fee5bc
--- /dev/null
+++ b/riscv/insns/c_beqz.h
@@ -0,0 +1,3 @@
+require_rvc;
+if (RVC_RS1S == 0)
+  set_pc(pc + insn.rvc_b_imm());
diff --git a/riscv/insns/c_bnez.h b/riscv/insns/c_bnez.h
new file mode 100644
index 0000000..a1a5666
--- /dev/null
+++ b/riscv/insns/c_bnez.h
@@ -0,0 +1,3 @@
+require_rvc;
+if (RVC_RS1S != 0)
+  set_pc(pc + insn.rvc_b_imm());
diff --git a/riscv/insns/c_j.h b/riscv/insns/c_j.h
new file mode 100644
index 0000000..f57022d
--- /dev/null
+++ b/riscv/insns/c_j.h
@@ -0,0 +1,2 @@
+require_rvc;
+set_pc(pc + insn.rvc_j_imm());
diff --git a/riscv/insns/c_jalr.h b/riscv/insns/c_jalr.h
new file mode 100644
index 0000000..9fd7f5d
--- /dev/null
+++ b/riscv/insns/c_jalr.h
@@ -0,0 +1,4 @@
+require_rvc;
+reg_t tmp = npc;
+set_pc(RVC_RS1 & ~reg_t(1));
+WRITE_RD(tmp);
diff --git a/riscv/insns/c_ld.h b/riscv/insns/c_ld.h
new file mode 100644
index 0000000..37b0ee2
--- /dev/null
+++ b/riscv/insns/c_ld.h
@@ -0,0 +1,3 @@
+require_rvc;
+require_rv64;
+WRITE_RVC_RDS(MMU.load_int64(RVC_RS1S + insn.rvc_ld_imm()));
diff --git a/riscv/insns/c_ldsp.h b/riscv/insns/c_ldsp.h
new file mode 100644
index 0000000..0b8bcbe
--- /dev/null
+++ b/riscv/insns/c_ldsp.h
@@ -0,0 +1,3 @@
+require_rvc;
+require_rv64;
+WRITE_RD(MMU.load_int64(RVC_SP + insn.rvc_ldsp_imm()));
diff --git a/riscv/insns/c_li.h b/riscv/insns/c_li.h
new file mode 100644
index 0000000..b53c958
--- /dev/null
+++ b/riscv/insns/c_li.h
@@ -0,0 +1,7 @@
+require_rvc;
+if (insn.rvc_rd() == 0) {
+  if (insn.rvc_imm() == -32) // c.sbreak
+    throw trap_breakpoint();
+  throw trap_illegal_instruction();
+} else // c.li
+  WRITE_RD(insn.rvc_imm());
diff --git a/riscv/insns/c_lui.h b/riscv/insns/c_lui.h
new file mode 100644
index 0000000..abdb78e
--- /dev/null
+++ b/riscv/insns/c_lui.h
@@ -0,0 +1,2 @@
+require_rvc;
+WRITE_RD(insn.rvc_imm() << 12);
diff --git a/riscv/insns/c_lw.h b/riscv/insns/c_lw.h
new file mode 100644
index 0000000..9c6f470
--- /dev/null
+++ b/riscv/insns/c_lw.h
@@ -0,0 +1,2 @@
+require_rvc;
+WRITE_RVC_RDS(MMU.load_int32(RVC_RS1S + insn.rvc_lw_imm()));
diff --git a/riscv/insns/c_lwsp.h b/riscv/insns/c_lwsp.h
new file mode 100644
index 0000000..8d9b9e3
--- /dev/null
+++ b/riscv/insns/c_lwsp.h
@@ -0,0 +1,2 @@
+require_rvc;
+WRITE_RD(MMU.load_int32(RVC_SP + insn.rvc_lwsp_imm()));
diff --git a/riscv/insns/c_mv.h b/riscv/insns/c_mv.h
new file mode 100644
index 0000000..6de6584
--- /dev/null
+++ b/riscv/insns/c_mv.h
@@ -0,0 +1,2 @@
+require_rvc;
+WRITE_RD(RVC_RS1);
diff --git a/riscv/insns/c_sd.h b/riscv/insns/c_sd.h
new file mode 100644
index 0000000..13de934
--- /dev/null
+++ b/riscv/insns/c_sd.h
@@ -0,0 +1,3 @@
+require_rvc;
+require_rv64;
+MMU.store_uint64(RVC_RS1S + insn.rvc_ld_imm(), RVC_RS2S);
diff --git a/riscv/insns/c_sdsp.h b/riscv/insns/c_sdsp.h
new file mode 100644
index 0000000..6028b0f
--- /dev/null
+++ b/riscv/insns/c_sdsp.h
@@ -0,0 +1,3 @@
+require_rvc;
+require_rv64;
+MMU.store_uint64(RVC_SP + insn.rvc_ldsp_imm(), RVC_RS2);
diff --git a/riscv/insns/c_slli.h b/riscv/insns/c_slli.h
new file mode 100644
index 0000000..fb6dffd
--- /dev/null
+++ b/riscv/insns/c_slli.h
@@ -0,0 +1,4 @@
+require_rvc;
+if (insn.rvc_imm() >= xlen)
+  throw trap_illegal_instruction();
+WRITE_RD(sext_xlen(RVC_RS2 << insn.rvc_imm()));
diff --git a/riscv/insns/c_sw.h b/riscv/insns/c_sw.h
new file mode 100644
index 0000000..34deb9d
--- /dev/null
+++ b/riscv/insns/c_sw.h
@@ -0,0 +1,2 @@
+require_rvc;
+MMU.store_uint32(RVC_RS1S + insn.rvc_lw_imm(), RVC_RS2S);
diff --git a/riscv/insns/c_swsp.h b/riscv/insns/c_swsp.h
new file mode 100644
index 0000000..bbb5ad0
--- /dev/null
+++ b/riscv/insns/c_swsp.h
@@ -0,0 +1,2 @@
+require_rvc;
+MMU.store_uint32(RVC_SP + insn.rvc_lwsp_imm(), RVC_RS2);
diff --git a/riscv/insns/slli.h b/riscv/insns/slli.h
index 7291276..dfe7168 100644
--- a/riscv/insns/slli.h
+++ b/riscv/insns/slli.h
@@ -1,8 +1,3 @@
-if (xlen == 64)
-  WRITE_RD(RS1 << SHAMT);
-else
-{
-  if(SHAMT & 0x20)
-    throw trap_illegal_instruction();
-  WRITE_RD(sext32(RS1 << SHAMT));
-}
+if (SHAMT >= xlen)
+  throw trap_illegal_instruction();
+WRITE_RD(sext_xlen(RS1 << SHAMT));