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| author | Andrew Waterman <waterman@s144.Millennium.Berkeley.EDU> | 2011-05-18 16:09:45 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@s144.Millennium.Berkeley.EDU> | 2011-05-18 16:09:45 -0700 |
| commit | 6928933df6ab7f12bc7f0564661368630d9789c3 (patch) | |
| tree | ce6c40bbabbf60b3ba5dba56f70a1c323e9e134c /riscv/insns | |
| parent | dd1da1656719e9304fde74758c7bb8038bb82025 (diff) | |
| download | spike-6928933df6ab7f12bc7f0564661368630d9789c3.zip spike-6928933df6ab7f12bc7f0564661368630d9789c3.tar.gz spike-6928933df6ab7f12bc7f0564661368630d9789c3.tar.bz2 | |
[sim] fixed fcvt rounding bugs
Diffstat (limited to 'riscv/insns')
| -rw-r--r-- | riscv/insns/fcvt_l_d.h | 2 | ||||
| -rw-r--r-- | riscv/insns/fcvt_l_s.h | 2 | ||||
| -rw-r--r-- | riscv/insns/fcvt_lu_d.h | 2 | ||||
| -rw-r--r-- | riscv/insns/fcvt_lu_s.h | 2 | ||||
| -rw-r--r-- | riscv/insns/fcvt_w_d.h | 2 | ||||
| -rw-r--r-- | riscv/insns/fcvt_w_s.h | 2 | ||||
| -rw-r--r-- | riscv/insns/fcvt_wu_d.h | 2 | ||||
| -rw-r--r-- | riscv/insns/fcvt_wu_s.h | 2 |
8 files changed, 8 insertions, 8 deletions
diff --git a/riscv/insns/fcvt_l_d.h b/riscv/insns/fcvt_l_d.h index bd460d5..206ba4f 100644 --- a/riscv/insns/fcvt_l_d.h +++ b/riscv/insns/fcvt_l_d.h @@ -1,5 +1,5 @@ require_xpr64; require_fp; softfloat_roundingMode = RM; -RD = f64_to_i64_r_minMag(FRS1,true); +RD = f64_to_i64(FRS1, RM, true); set_fp_exceptions; diff --git a/riscv/insns/fcvt_l_s.h b/riscv/insns/fcvt_l_s.h index 1ed4594..e05f476 100644 --- a/riscv/insns/fcvt_l_s.h +++ b/riscv/insns/fcvt_l_s.h @@ -1,5 +1,5 @@ require_xpr64; require_fp; softfloat_roundingMode = RM; -RD = f32_to_i64_r_minMag(FRS1,true); +RD = f32_to_i64(FRS1, RM, true); set_fp_exceptions; diff --git a/riscv/insns/fcvt_lu_d.h b/riscv/insns/fcvt_lu_d.h index bd460d5..44c3dd6 100644 --- a/riscv/insns/fcvt_lu_d.h +++ b/riscv/insns/fcvt_lu_d.h @@ -1,5 +1,5 @@ require_xpr64; require_fp; softfloat_roundingMode = RM; -RD = f64_to_i64_r_minMag(FRS1,true); +RD = f64_to_ui64(FRS1, RM, true); set_fp_exceptions; diff --git a/riscv/insns/fcvt_lu_s.h b/riscv/insns/fcvt_lu_s.h index 1ed4594..13de436 100644 --- a/riscv/insns/fcvt_lu_s.h +++ b/riscv/insns/fcvt_lu_s.h @@ -1,5 +1,5 @@ require_xpr64; require_fp; softfloat_roundingMode = RM; -RD = f32_to_i64_r_minMag(FRS1,true); +RD = f32_to_ui64(FRS1, RM, true); set_fp_exceptions; diff --git a/riscv/insns/fcvt_w_d.h b/riscv/insns/fcvt_w_d.h index e924467..88dc3d3 100644 --- a/riscv/insns/fcvt_w_d.h +++ b/riscv/insns/fcvt_w_d.h @@ -1,4 +1,4 @@ require_fp; softfloat_roundingMode = RM; -RD = f64_to_i32_r_minMag(FRS1,true); +RD = sext32(f64_to_i32(FRS1, RM, true)); set_fp_exceptions; diff --git a/riscv/insns/fcvt_w_s.h b/riscv/insns/fcvt_w_s.h index 809797f..f14cc19 100644 --- a/riscv/insns/fcvt_w_s.h +++ b/riscv/insns/fcvt_w_s.h @@ -1,4 +1,4 @@ require_fp; softfloat_roundingMode = RM; -RD = f32_to_i32_r_minMag(FRS1,true); +RD = sext32(f32_to_i32(FRS1, RM, true)); set_fp_exceptions; diff --git a/riscv/insns/fcvt_wu_d.h b/riscv/insns/fcvt_wu_d.h index 93860e8..43ad6f6 100644 --- a/riscv/insns/fcvt_wu_d.h +++ b/riscv/insns/fcvt_wu_d.h @@ -1,4 +1,4 @@ require_fp; softfloat_roundingMode = RM; -RD = f64_to_ui32_r_minMag(FRS1,true); +RD = sext32(f64_to_ui32(FRS1, RM, true)); set_fp_exceptions; diff --git a/riscv/insns/fcvt_wu_s.h b/riscv/insns/fcvt_wu_s.h index 04b8fb2..ff7a11c 100644 --- a/riscv/insns/fcvt_wu_s.h +++ b/riscv/insns/fcvt_wu_s.h @@ -1,4 +1,4 @@ require_fp; softfloat_roundingMode = RM; -RD = f32_to_ui32_r_minMag(FRS1,true); +RD = sext32(f32_to_ui32(FRS1, RM, true)); set_fp_exceptions; |