Implement clearing-misa.C-while-PC-is-misaligned proposal

See https://github.com/riscv/riscv-isa-manual/pull/139

Not adopted yet, but I'm putting the implementation here for reference.

6 files changed, 6 insertions, 0 deletions

diff --git a/riscv/insns/csrrc.h b/riscv/insns/csrrc.h
index eae91fe..0472d80 100644
--- a/riscv/insns/csrrc.h
+++ b/riscv/insns/csrrc.h
@@ -5,3 +5,4 @@ if (write) {
   p->set_csr(csr, old & ~RS1);
 }
 WRITE_RD(sext_xlen(old));
+serialize();
diff --git a/riscv/insns/csrrci.h b/riscv/insns/csrrci.h
index 986d601..4d83cc0 100644
--- a/riscv/insns/csrrci.h
+++ b/riscv/insns/csrrci.h
@@ -5,3 +5,4 @@ if (write) {
   p->set_csr(csr, old & ~(reg_t)insn.rs1());
 }
 WRITE_RD(sext_xlen(old));
+serialize();
diff --git a/riscv/insns/csrrs.h b/riscv/insns/csrrs.h
index ec61b42..4e8bde9 100644
--- a/riscv/insns/csrrs.h
+++ b/riscv/insns/csrrs.h
@@ -5,3 +5,4 @@ if (write) {
   p->set_csr(csr, old | RS1);
 }
 WRITE_RD(sext_xlen(old));
+serialize();
diff --git a/riscv/insns/csrrsi.h b/riscv/insns/csrrsi.h
index aa44dcc..b673725 100644
--- a/riscv/insns/csrrsi.h
+++ b/riscv/insns/csrrsi.h
@@ -5,3 +5,4 @@ if (write) {
   p->set_csr(csr, old | insn.rs1());
 }
 WRITE_RD(sext_xlen(old));
+serialize();
diff --git a/riscv/insns/csrrw.h b/riscv/insns/csrrw.h
index 9f2324f..e45420b 100644
--- a/riscv/insns/csrrw.h
+++ b/riscv/insns/csrrw.h
@@ -2,3 +2,4 @@ int csr = validate_csr(insn.csr(), true);
 reg_t old = p->get_csr(csr);
 p->set_csr(csr, RS1);
 WRITE_RD(sext_xlen(old));
+serialize();
diff --git a/riscv/insns/csrrwi.h b/riscv/insns/csrrwi.h
index cf0710f..decadf4 100644
--- a/riscv/insns/csrrwi.h
+++ b/riscv/insns/csrrwi.h
@@ -2,3 +2,4 @@ int csr = validate_csr(insn.csr(), true);
 reg_t old = p->get_csr(csr);
 p->set_csr(csr, insn.rs1());
 WRITE_RD(sext_xlen(old));
+serialize();