Instructions are no longer member functions

51 files changed, 84 insertions, 78 deletions

diff --git a/riscv/insns/amoadd_d.h b/riscv/insns/amoadd_d.h
index b8450bf..bba975c 100644
--- a/riscv/insns/amoadd_d.h
+++ b/riscv/insns/amoadd_d.h
@@ -1,4 +1,4 @@
 require_xpr64;
-reg_t v = mmu.load_uint64(RS1);
-mmu.store_uint64(RS1, RS2 + v);
+reg_t v = MMU.load_uint64(RS1);
+MMU.store_uint64(RS1, RS2 + v);
 RD = v;
diff --git a/riscv/insns/amoadd_w.h b/riscv/insns/amoadd_w.h
index 033b3c8..07c9c9a 100644
--- a/riscv/insns/amoadd_w.h
+++ b/riscv/insns/amoadd_w.h
@@ -1,3 +1,3 @@
-reg_t v = mmu.load_int32(RS1);
-mmu.store_uint32(RS1, RS2 + v);
+reg_t v = MMU.load_int32(RS1);
+MMU.store_uint32(RS1, RS2 + v);
 RD = v;
diff --git a/riscv/insns/amoand_d.h b/riscv/insns/amoand_d.h
index 586eb7f..1bb3402 100644
--- a/riscv/insns/amoand_d.h
+++ b/riscv/insns/amoand_d.h
@@ -1,4 +1,4 @@
 require_xpr64;
-reg_t v = mmu.load_uint64(RS1);
-mmu.store_uint64(RS1, RS2 & v);
+reg_t v = MMU.load_uint64(RS1);
+MMU.store_uint64(RS1, RS2 & v);
 RD = v;
diff --git a/riscv/insns/amoand_w.h b/riscv/insns/amoand_w.h
index 18a9249..91866dc 100644
--- a/riscv/insns/amoand_w.h
+++ b/riscv/insns/amoand_w.h
@@ -1,3 +1,3 @@
-reg_t v = mmu.load_int32(RS1);
-mmu.store_uint32(RS1, RS2 & v);
+reg_t v = MMU.load_int32(RS1);
+MMU.store_uint32(RS1, RS2 & v);
 RD = v;
diff --git a/riscv/insns/amomax_d.h b/riscv/insns/amomax_d.h
index 1a0bc8a..dfd2b33 100644
--- a/riscv/insns/amomax_d.h
+++ b/riscv/insns/amomax_d.h
@@ -1,4 +1,4 @@
 require_xpr64;
-sreg_t v = mmu.load_int64(RS1);
-mmu.store_uint64(RS1, std::max(sreg_t(RS2),v));
+sreg_t v = MMU.load_int64(RS1);
+MMU.store_uint64(RS1, std::max(sreg_t(RS2),v));
 RD = v;
diff --git a/riscv/insns/amomax_w.h b/riscv/insns/amomax_w.h
index ff9c2da..1f68a8b 100644
--- a/riscv/insns/amomax_w.h
+++ b/riscv/insns/amomax_w.h
@@ -1,3 +1,3 @@
-int32_t v = mmu.load_int32(RS1);
-mmu.store_uint32(RS1, std::max(int32_t(RS2),v));
+int32_t v = MMU.load_int32(RS1);
+MMU.store_uint32(RS1, std::max(int32_t(RS2),v));
 RD = v;
diff --git a/riscv/insns/amomaxu_d.h b/riscv/insns/amomaxu_d.h
index ccfaf1d..8d50a0a 100644
--- a/riscv/insns/amomaxu_d.h
+++ b/riscv/insns/amomaxu_d.h
@@ -1,4 +1,4 @@
 require_xpr64;
-reg_t v = mmu.load_uint64(RS1);
-mmu.store_uint64(RS1, std::max(RS2,v));
+reg_t v = MMU.load_uint64(RS1);
+MMU.store_uint64(RS1, std::max(RS2,v));
 RD = v;
diff --git a/riscv/insns/amomaxu_w.h b/riscv/insns/amomaxu_w.h
index 075847d..d507e4f 100644
--- a/riscv/insns/amomaxu_w.h
+++ b/riscv/insns/amomaxu_w.h
@@ -1,3 +1,3 @@
-uint32_t v = mmu.load_int32(RS1);
-mmu.store_uint32(RS1, std::max(uint32_t(RS2),v));
+uint32_t v = MMU.load_int32(RS1);
+MMU.store_uint32(RS1, std::max(uint32_t(RS2),v));
 RD = (int32_t)v;
diff --git a/riscv/insns/amomin_d.h b/riscv/insns/amomin_d.h
index 4f3b6d6..a20ace8 100644
--- a/riscv/insns/amomin_d.h
+++ b/riscv/insns/amomin_d.h
@@ -1,4 +1,4 @@
 require_xpr64;
-sreg_t v = mmu.load_int64(RS1);
-mmu.store_uint64(RS1, std::min(sreg_t(RS2),v));
+sreg_t v = MMU.load_int64(RS1);
+MMU.store_uint64(RS1, std::min(sreg_t(RS2),v));
 RD = v;
diff --git a/riscv/insns/amomin_w.h b/riscv/insns/amomin_w.h
index 529ad50..d8f95af 100644
--- a/riscv/insns/amomin_w.h
+++ b/riscv/insns/amomin_w.h
@@ -1,3 +1,3 @@
-int32_t v = mmu.load_int32(RS1);
-mmu.store_uint32(RS1, std::min(int32_t(RS2),v));
+int32_t v = MMU.load_int32(RS1);
+MMU.store_uint32(RS1, std::min(int32_t(RS2),v));
 RD = v;
diff --git a/riscv/insns/amominu_d.h b/riscv/insns/amominu_d.h
index c09c51a..4f83c0f 100644
--- a/riscv/insns/amominu_d.h
+++ b/riscv/insns/amominu_d.h
@@ -1,4 +1,4 @@
 require_xpr64;
-reg_t v = mmu.load_uint64(RS1);
-mmu.store_uint64(RS1, std::min(RS2,v));
+reg_t v = MMU.load_uint64(RS1);
+MMU.store_uint64(RS1, std::min(RS2,v));
 RD = v;
diff --git a/riscv/insns/amominu_w.h b/riscv/insns/amominu_w.h
index d8d6377..a3a537a 100644
--- a/riscv/insns/amominu_w.h
+++ b/riscv/insns/amominu_w.h
@@ -1,3 +1,3 @@
-uint32_t v = mmu.load_int32(RS1);
-mmu.store_uint32(RS1, std::min(uint32_t(RS2),v));
+uint32_t v = MMU.load_int32(RS1);
+MMU.store_uint32(RS1, std::min(uint32_t(RS2),v));
 RD = (int32_t)v;
diff --git a/riscv/insns/amoor_d.h b/riscv/insns/amoor_d.h
index 76a4508..87b6f2a 100644
--- a/riscv/insns/amoor_d.h
+++ b/riscv/insns/amoor_d.h
@@ -1,4 +1,4 @@
 require_xpr64;
-reg_t v = mmu.load_uint64(RS1);
-mmu.store_uint64(RS1, RS2 | v);
+reg_t v = MMU.load_uint64(RS1);
+MMU.store_uint64(RS1, RS2 | v);
 RD = v;
diff --git a/riscv/insns/amoor_w.h b/riscv/insns/amoor_w.h
index 741fbef..0733fad 100644
--- a/riscv/insns/amoor_w.h
+++ b/riscv/insns/amoor_w.h
@@ -1,3 +1,3 @@
-reg_t v = mmu.load_int32(RS1);
-mmu.store_uint32(RS1, RS2 | v);
+reg_t v = MMU.load_int32(RS1);
+MMU.store_uint32(RS1, RS2 | v);
 RD = v;
diff --git a/riscv/insns/amoswap_d.h b/riscv/insns/amoswap_d.h
index 43e3538..3423b91 100644
--- a/riscv/insns/amoswap_d.h
+++ b/riscv/insns/amoswap_d.h
@@ -1,4 +1,4 @@
 require_xpr64;
-reg_t v = mmu.load_uint64(RS1);
-mmu.store_uint64(RS1, RS2);
+reg_t v = MMU.load_uint64(RS1);
+MMU.store_uint64(RS1, RS2);
 RD = v;
diff --git a/riscv/insns/amoswap_w.h b/riscv/insns/amoswap_w.h
index 30e6102..b888235 100644
--- a/riscv/insns/amoswap_w.h
+++ b/riscv/insns/amoswap_w.h
@@ -1,3 +1,3 @@
-reg_t v = mmu.load_int32(RS1);
-mmu.store_uint32(RS1, RS2);
+reg_t v = MMU.load_int32(RS1);
+MMU.store_uint32(RS1, RS2);
 RD = v;
diff --git a/riscv/insns/break.h b/riscv/insns/break.h
index 7fd3d66..c22776c 100644
--- a/riscv/insns/break.h
+++ b/riscv/insns/break.h
@@ -1 +1 @@
-throw trap_breakpoint;
+throw trap_breakpoint();
diff --git a/riscv/insns/clearpcr.h b/riscv/insns/clearpcr.h
index 7acf221..56c3584 100644
--- a/riscv/insns/clearpcr.h
+++ b/riscv/insns/clearpcr.h
@@ -1,4 +1,2 @@
 require_supervisor;
-reg_t temp = get_pcr(insn.rtype.rs1);
-set_pcr(insn.rtype.rs1, temp & ~SIMM);
-RD = temp;
+RD = p->set_pcr(insn.rtype.rs1, p->get_pcr(insn.rtype.rs1) & ~SIMM);
diff --git a/riscv/insns/eret.h b/riscv/insns/eret.h
index 9ea8baf..d4517ee 100644
--- a/riscv/insns/eret.h
+++ b/riscv/insns/eret.h
@@ -1,5 +1,5 @@
 require_supervisor;
-set_pcr(PCR_SR, ((sr & ~(SR_S | SR_EI)) |
-                ((sr & SR_PS) ? SR_S : 0)) |
-                ((sr & SR_PEI) ? SR_EI : 0));
-set_pc(epc);
+p->set_pcr(PCR_SR, ((p->get_state()->sr & ~(SR_S | SR_EI)) |
+                ((p->get_state()->sr & SR_PS) ? SR_S : 0)) |
+                ((p->get_state()->sr & SR_PEI) ? SR_EI : 0));
+set_pc(p->get_state()->epc);
diff --git a/riscv/insns/fence_i.h b/riscv/insns/fence_i.h
index a2dbffe..38dcaf3 100644
--- a/riscv/insns/fence_i.h
+++ b/riscv/insns/fence_i.h
@@ -1 +1 @@
-mmu.flush_icache();
+MMU.flush_icache();
diff --git a/riscv/insns/fld.h b/riscv/insns/fld.h
index bc8b9c7..2704a4d 100644
--- a/riscv/insns/fld.h
+++ b/riscv/insns/fld.h
@@ -1,2 +1,2 @@
 require_fp;
-FRD = mmu.load_int64(ITYPE_EADDR);
+FRD = MMU.load_int64(ITYPE_EADDR);
diff --git a/riscv/insns/flw.h b/riscv/insns/flw.h
index 74374b9..afab636 100644
--- a/riscv/insns/flw.h
+++ b/riscv/insns/flw.h
@@ -1,2 +1,2 @@
 require_fp;
-FRD = mmu.load_int32(ITYPE_EADDR);
+FRD = MMU.load_int32(ITYPE_EADDR);
diff --git a/riscv/insns/frsr.h b/riscv/insns/frsr.h
index 29debc4..ef121e3 100644
--- a/riscv/insns/frsr.h
+++ b/riscv/insns/frsr.h
@@ -1,2 +1,2 @@
 require_fp;
-RD = fsr;
+RD = p->get_fsr();
diff --git a/riscv/insns/fsd.h b/riscv/insns/fsd.h
index 95fbd26..0e1c38a 100644
--- a/riscv/insns/fsd.h
+++ b/riscv/insns/fsd.h
@@ -1,2 +1,2 @@
 require_fp;
-mmu.store_uint64(BTYPE_EADDR, FRS2);
+MMU.store_uint64(BTYPE_EADDR, FRS2);
diff --git a/riscv/insns/fssr.h b/riscv/insns/fssr.h
index cc6f9ea..a9acca6 100644
--- a/riscv/insns/fssr.h
+++ b/riscv/insns/fssr.h
@@ -1,4 +1,2 @@
 require_fp;
-uint32_t tmp = fsr;
-set_fsr(RS1);
-RD = tmp;
+RD = p->set_fsr(RS1);
diff --git a/riscv/insns/fsw.h b/riscv/insns/fsw.h
index 59d9066..c921123 100644
--- a/riscv/insns/fsw.h
+++ b/riscv/insns/fsw.h
@@ -1,2 +1,2 @@
 require_fp;
-mmu.store_uint32(BTYPE_EADDR, FRS2);
+MMU.store_uint32(BTYPE_EADDR, FRS2);
diff --git a/riscv/insns/lb.h b/riscv/insns/lb.h
index c88ee2d..56a5f32 100644
--- a/riscv/insns/lb.h
+++ b/riscv/insns/lb.h
@@ -1 +1 @@
-RD = mmu.load_int8(ITYPE_EADDR);
+RD = MMU.load_int8(ITYPE_EADDR);
diff --git a/riscv/insns/lbu.h b/riscv/insns/lbu.h
index bcef96b..66621c0 100644
--- a/riscv/insns/lbu.h
+++ b/riscv/insns/lbu.h
@@ -1 +1 @@
-RD = mmu.load_uint8(ITYPE_EADDR);
+RD = MMU.load_uint8(ITYPE_EADDR);
diff --git a/riscv/insns/ld.h b/riscv/insns/ld.h
index 2bbe5c3..f214294 100644
--- a/riscv/insns/ld.h
+++ b/riscv/insns/ld.h
@@ -1,2 +1,2 @@
 require_xpr64;
-RD = mmu.load_int64(ITYPE_EADDR);
+RD = MMU.load_int64(ITYPE_EADDR);
diff --git a/riscv/insns/lh.h b/riscv/insns/lh.h
index c04302c..fea2a8e 100644
--- a/riscv/insns/lh.h
+++ b/riscv/insns/lh.h
@@ -1 +1 @@
-RD = mmu.load_int16(ITYPE_EADDR);
+RD = MMU.load_int16(ITYPE_EADDR);
diff --git a/riscv/insns/lhu.h b/riscv/insns/lhu.h
index 99d0985..71c21be 100644
--- a/riscv/insns/lhu.h
+++ b/riscv/insns/lhu.h
@@ -1 +1 @@
-RD = mmu.load_uint16(ITYPE_EADDR);
+RD = MMU.load_uint16(ITYPE_EADDR);
diff --git a/riscv/insns/lr_d.h b/riscv/insns/lr_d.h
index 5c8eff1..3d2aace 100644
--- a/riscv/insns/lr_d.h
+++ b/riscv/insns/lr_d.h
@@ -1,2 +1,3 @@
 require_xpr64;
-RD = mmu.load_reserved_int64(RS1);
+p->get_state()->load_reservation = RS1;
+RD = MMU.load_int64(RS1);
diff --git a/riscv/insns/lr_w.h b/riscv/insns/lr_w.h
index 3ac4746..7ff48ea 100644
--- a/riscv/insns/lr_w.h
+++ b/riscv/insns/lr_w.h
@@ -1 +1,2 @@
-RD = mmu.load_reserved_int32(RS1);
+p->get_state()->load_reservation = RS1;
+RD = MMU.load_int32(RS1);
diff --git a/riscv/insns/lw.h b/riscv/insns/lw.h
index 639d0e7..77f735e 100644
--- a/riscv/insns/lw.h
+++ b/riscv/insns/lw.h
@@ -1 +1 @@
-RD = mmu.load_int32(ITYPE_EADDR);
+RD = MMU.load_int32(ITYPE_EADDR);
diff --git a/riscv/insns/lwu.h b/riscv/insns/lwu.h
index b3ebc0c..e731178 100644
--- a/riscv/insns/lwu.h
+++ b/riscv/insns/lwu.h
@@ -1,2 +1,2 @@
 require_xpr64;
-RD = mmu.load_uint32(ITYPE_EADDR);
+RD = MMU.load_uint32(ITYPE_EADDR);
diff --git a/riscv/insns/mfpcr.h b/riscv/insns/mfpcr.h
index f7aea9f..0f23426 100644
--- a/riscv/insns/mfpcr.h
+++ b/riscv/insns/mfpcr.h
@@ -1,2 +1,2 @@
 require_supervisor;
-RD = get_pcr(insn.rtype.rs1);
+RD = p->get_pcr(insn.rtype.rs1);
diff --git a/riscv/insns/mtpcr.h b/riscv/insns/mtpcr.h
index 5cd0134..770dfd5 100644
--- a/riscv/insns/mtpcr.h
+++ b/riscv/insns/mtpcr.h
@@ -1,4 +1,2 @@
 require_supervisor;
-reg_t val = get_pcr(insn.rtype.rs1);
-set_pcr(insn.rtype.rs1, RS2);
-RD = val;
+RD = p->set_pcr(insn.rtype.rs1, RS2);
diff --git a/riscv/insns/rdcycle.h b/riscv/insns/rdcycle.h
index 9b966a6..7ebe986 100644
--- a/riscv/insns/rdcycle.h
+++ b/riscv/insns/rdcycle.h
@@ -1 +1 @@
-RD = cycle;
+RD = sext_xprlen(p->get_state()->cycle);
diff --git a/riscv/insns/rdinstret.h b/riscv/insns/rdinstret.h
index 9b966a6..df56cb7 100644
--- a/riscv/insns/rdinstret.h
+++ b/riscv/insns/rdinstret.h
@@ -1 +1 @@
-RD = cycle;
+#include "insns/rdcycle.h"
diff --git a/riscv/insns/rdtime.h b/riscv/insns/rdtime.h
index 9b966a6..df56cb7 100644
--- a/riscv/insns/rdtime.h
+++ b/riscv/insns/rdtime.h
@@ -1 +1 @@
-RD = cycle;
+#include "insns/rdcycle.h"
diff --git a/riscv/insns/sb.h b/riscv/insns/sb.h
index 54176c0..db4d523 100644
--- a/riscv/insns/sb.h
+++ b/riscv/insns/sb.h
@@ -1 +1 @@
-mmu.store_uint8(BTYPE_EADDR, RS2);
+MMU.store_uint8(BTYPE_EADDR, RS2);
diff --git a/riscv/insns/sc_d.h b/riscv/insns/sc_d.h
index a29b9f7..9ad962c 100644
--- a/riscv/insns/sc_d.h
+++ b/riscv/insns/sc_d.h
@@ -1,2 +1,8 @@
 require_xpr64;
-RD = mmu.store_conditional_uint64(RS1, RS2);
+if (RS1 == p->get_state()->load_reservation)
+{
+  MMU.store_uint64(RS1, RS2);
+  RD = 0;
+}
+else
+  RD = 1;
diff --git a/riscv/insns/sc_w.h b/riscv/insns/sc_w.h
index caf7683..3ad79ac 100644
--- a/riscv/insns/sc_w.h
+++ b/riscv/insns/sc_w.h
@@ -1 +1,7 @@
-RD = mmu.store_conditional_uint32(RS1, RS2);
+if (RS1 == p->get_state()->load_reservation)
+{
+  MMU.store_uint32(RS1, RS2);
+  RD = 0;
+}
+else
+  RD = 1;
diff --git a/riscv/insns/sd.h b/riscv/insns/sd.h
index 558428e..24c0de9 100644
--- a/riscv/insns/sd.h
+++ b/riscv/insns/sd.h
@@ -1,2 +1,2 @@
 require_xpr64;
-mmu.store_uint64(BTYPE_EADDR, RS2);
+MMU.store_uint64(BTYPE_EADDR, RS2);
diff --git a/riscv/insns/setpcr.h b/riscv/insns/setpcr.h
index d645626..4a25d80 100644
--- a/riscv/insns/setpcr.h
+++ b/riscv/insns/setpcr.h
@@ -1,4 +1,2 @@
 require_supervisor;
-reg_t temp = get_pcr(insn.rtype.rs1);
-set_pcr(insn.rtype.rs1, temp | SIMM);
-RD = temp;
+RD = p->set_pcr(insn.rtype.rs1, p->get_pcr(insn.rtype.rs1) | SIMM);
diff --git a/riscv/insns/sh.h b/riscv/insns/sh.h
index 235e50e..69234dc 100644
--- a/riscv/insns/sh.h
+++ b/riscv/insns/sh.h
@@ -1 +1 @@
-mmu.store_uint16(BTYPE_EADDR, RS2);
+MMU.store_uint16(BTYPE_EADDR, RS2);
diff --git a/riscv/insns/slli.h b/riscv/insns/slli.h
index bfaf430..151d970 100644
--- a/riscv/insns/slli.h
+++ b/riscv/insns/slli.h
@@ -3,6 +3,6 @@ if(xpr64)
 else
 {
   if(SHAMT & 0x20)
-    throw trap_illegal_instruction;
+    throw trap_illegal_instruction();
   RD = sext32(RS1 << SHAMT);
 }
diff --git a/riscv/insns/srai.h b/riscv/insns/srai.h
index bb17d27..7360d5f 100644
--- a/riscv/insns/srai.h
+++ b/riscv/insns/srai.h
@@ -3,6 +3,6 @@ if(xpr64)
 else
 {
   if(SHAMT & 0x20)
-    throw trap_illegal_instruction;
+    throw trap_illegal_instruction();
   RD = sext32(int32_t(RS1) >> SHAMT);
 }
diff --git a/riscv/insns/srli.h b/riscv/insns/srli.h
index 5378fd1..f5b8c02 100644
--- a/riscv/insns/srli.h
+++ b/riscv/insns/srli.h
@@ -3,6 +3,6 @@ if(xpr64)
 else
 {
   if(SHAMT & 0x20)
-    throw trap_illegal_instruction;
+    throw trap_illegal_instruction();
   RD = sext32((uint32_t)RS1 >> SHAMT);
 }
diff --git a/riscv/insns/sw.h b/riscv/insns/sw.h
index 008d8c0..81ca71d 100644
--- a/riscv/insns/sw.h
+++ b/riscv/insns/sw.h
@@ -1 +1 @@
-mmu.store_uint32(BTYPE_EADDR, RS2);
+MMU.store_uint32(BTYPE_EADDR, RS2);
diff --git a/riscv/insns/syscall.h b/riscv/insns/syscall.h
index 2c7199d..b31b7e6 100644
--- a/riscv/insns/syscall.h
+++ b/riscv/insns/syscall.h
@@ -1 +1 @@
-throw trap_syscall;
+throw trap_syscall();