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| author | Dave.Wen <dave.wen@sifive.com> | 2019-04-30 19:27:33 -0700 |
|---|---|---|
| committer | Dave.Wen <dave.wen@sifive.com> | 2019-04-30 19:27:33 -0700 |
| commit | e7a3f6e7f4a847f750830efcbc051354d282d750 (patch) | |
| tree | 72dd63660fd020d0fe5a7c8b2247b15d120ea6c2 /riscv/insns | |
| parent | 65ba44dccfc9d02e5723a467eefd47ac47295e60 (diff) | |
| download | spike-e7a3f6e7f4a847f750830efcbc051354d282d750.zip spike-e7a3f6e7f4a847f750830efcbc051354d282d750.tar.gz spike-e7a3f6e7f4a847f750830efcbc051354d282d750.tar.bz2 | |
rvv: decouple the vectorUnit to the processor's state.
Diffstat (limited to 'riscv/insns')
110 files changed, 563 insertions, 563 deletions
diff --git a/riscv/insns/csrrc.h b/riscv/insns/csrrc.h index b87c587..bf01a87 100644 --- a/riscv/insns/csrrc.h +++ b/riscv/insns/csrrc.h @@ -2,9 +2,9 @@ bool write = insn.rs1() != 0; int csr = validate_csr(insn.csr(), write); reg_t old; if (check_vcsr(csr)) { - old = STATE.VU.get_vcsr(csr); + old = p->VU.get_vcsr(csr); if (write) { - STATE.VU.set_vcsr(csr, old & ~RS1); + p->VU.set_vcsr(csr, old & ~RS1); } }else{ old = p->get_csr(csr); diff --git a/riscv/insns/csrrci.h b/riscv/insns/csrrci.h index bb8d042..2ebb8c3 100644 --- a/riscv/insns/csrrci.h +++ b/riscv/insns/csrrci.h @@ -2,9 +2,9 @@ bool write = insn.rs1() != 0; int csr = validate_csr(insn.csr(), write); reg_t old; if (check_vcsr(csr)) { - old = STATE.VU.get_vcsr(csr); + old = p->VU.get_vcsr(csr); if (write) { - STATE.VU.set_vcsr(csr, old & ~(reg_t)insn.rs1()); + p->VU.set_vcsr(csr, old & ~(reg_t)insn.rs1()); } }else{ old = p->get_csr(csr); diff --git a/riscv/insns/csrrs.h b/riscv/insns/csrrs.h index 506cc42..2e3c95d 100644 --- a/riscv/insns/csrrs.h +++ b/riscv/insns/csrrs.h @@ -2,9 +2,9 @@ bool write = insn.rs1() != 0; int csr = validate_csr(insn.csr(), write); reg_t old; if (check_vcsr(csr)) { - old = STATE.VU.get_vcsr(csr); + old = p->VU.get_vcsr(csr); if (write) { - STATE.VU.set_vcsr(csr, old | RS1); + p->VU.set_vcsr(csr, old | RS1); } }else{ old = p->get_csr(csr); diff --git a/riscv/insns/csrrsi.h b/riscv/insns/csrrsi.h index 55d0eb3..cbdc3a1 100644 --- a/riscv/insns/csrrsi.h +++ b/riscv/insns/csrrsi.h @@ -2,9 +2,9 @@ bool write = insn.rs1() != 0; int csr = validate_csr(insn.csr(), write); reg_t old; if (check_vcsr(csr)) { - old = STATE.VU.get_vcsr(csr); + old = p->VU.get_vcsr(csr); if (write) { - STATE.VU.set_vcsr(csr, old | insn.rs1()); + p->VU.set_vcsr(csr, old | insn.rs1()); } }else{ old = p->get_csr(csr); diff --git a/riscv/insns/csrrw.h b/riscv/insns/csrrw.h index a0c84da..f1e5780 100644 --- a/riscv/insns/csrrw.h +++ b/riscv/insns/csrrw.h @@ -1,8 +1,8 @@ int csr = validate_csr(insn.csr(), true); reg_t old; if (check_vcsr(csr)) { - old = STATE.VU.get_vcsr(csr); - STATE.VU.set_vcsr(csr, RS1); + old = p->VU.get_vcsr(csr); + p->VU.set_vcsr(csr, RS1); }else{ old = p->get_csr(csr); p->set_csr(csr, RS1); diff --git a/riscv/insns/csrrwi.h b/riscv/insns/csrrwi.h index dd27d14..a3b4629 100644 --- a/riscv/insns/csrrwi.h +++ b/riscv/insns/csrrwi.h @@ -1,8 +1,8 @@ int csr = validate_csr(insn.csr(), true); reg_t old; if (check_vcsr(csr)) { - old = STATE.VU.get_vcsr(csr); - STATE.VU.set_vcsr(csr, insn.rs1()); + old = p->VU.get_vcsr(csr); + p->VU.set_vcsr(csr, insn.rs1()); }else{ old = p->get_csr(csr); p->set_csr(csr, insn.rs1()); diff --git a/riscv/insns/vaadd_vi.h b/riscv/insns/vaadd_vi.h index a4ce6bb..bed1c38 100644 --- a/riscv/insns/vaadd_vi.h +++ b/riscv/insns/vaadd_vi.h @@ -1,5 +1,5 @@ // vaadd: Averaging adds of integers -VRM xrm = STATE.VU.get_vround_mode(); +VRM xrm = p->VU.get_vround_mode(); VI_VI_LOOP ({ int64_t result = vsext(simm5, sew) + vsext(vs2, sew); diff --git a/riscv/insns/vaadd_vv.h b/riscv/insns/vaadd_vv.h index 735356d..d4b0f1b 100644 --- a/riscv/insns/vaadd_vv.h +++ b/riscv/insns/vaadd_vv.h @@ -1,5 +1,5 @@ // vaadd: Averaging adds of integers -VRM xrm = STATE.VU.get_vround_mode(); +VRM xrm = p->VU.get_vround_mode(); VI_VV_LOOP ({ int64_t result = vsext(vs1, sew) + vsext(vs2, sew); diff --git a/riscv/insns/vaadd_vx.h b/riscv/insns/vaadd_vx.h index d8655ab..6f8d50a 100644 --- a/riscv/insns/vaadd_vx.h +++ b/riscv/insns/vaadd_vx.h @@ -1,5 +1,5 @@ // vaadd: Averaging adds of integers -VRM xrm = STATE.VU.get_vround_mode(); +VRM xrm = p->VU.get_vround_mode(); VI_VX_LOOP ({ int64_t tval = vsext(rs1, sew) + vsext(vs2, sew); diff --git a/riscv/insns/vadc_vv.h b/riscv/insns/vadc_vv.h index e448302..eae6d82 100644 --- a/riscv/insns/vadc_vv.h +++ b/riscv/insns/vadc_vv.h @@ -2,9 +2,9 @@ // v0[i] = carry(vs1[i] + vs2[i] + v0[i].LSB) VI_VV_LOOP ({ - uint64_t &v0 = STATE.VU.elt<uint64_t>(0, i); + uint64_t &v0 = p->VU.elt<uint64_t>(0, i); int64_t sum = sext_xlen(vs1 + vs2); vd = sext_xlen(sum + (v0&1)); - if (sum > (1 << STATE.VU.vsew)) + if (sum > (1 << p->VU.vsew)) v0 |= 1; }) diff --git a/riscv/insns/vasub_vv.h b/riscv/insns/vasub_vv.h index 9380ef1..3a5a22d 100644 --- a/riscv/insns/vasub_vv.h +++ b/riscv/insns/vasub_vv.h @@ -1,5 +1,5 @@ // vasub: Averaging subs of integers -VRM xrm = STATE.VU.get_vround_mode(); +VRM xrm = p->VU.get_vround_mode(); VI_VV_LOOP ({ int64_t ret = (int64_t)vs2 - vs1; diff --git a/riscv/insns/vasub_vx.h b/riscv/insns/vasub_vx.h index 24547d6..7869006 100644 --- a/riscv/insns/vasub_vx.h +++ b/riscv/insns/vasub_vx.h @@ -1,5 +1,5 @@ // vasub: Averaging subs of integers -VRM xrm = STATE.VU.get_vround_mode(); +VRM xrm = p->VU.get_vround_mode(); VI_VX_LOOP ({ int64_t ret = (int64_t)vs2 - rs1; diff --git a/riscv/insns/vfadd_vf.h b/riscv/insns/vfadd_vf.h index 84237a5..566450e 100644 --- a/riscv/insns/vfadd_vf.h +++ b/riscv/insns/vfadd_vf.h @@ -1,7 +1,7 @@ // vfadd VFP_VF_LOOP ({ - switch(STATE.VU.vsew){ + switch(p->VU.vsew){ case e32: vd = f32_add(rs1, vs2); break; diff --git a/riscv/insns/vfadd_vv.h b/riscv/insns/vfadd_vv.h index 12fec1c..fedd05f 100644 --- a/riscv/insns/vfadd_vv.h +++ b/riscv/insns/vfadd_vv.h @@ -1,7 +1,7 @@ // vfadd VFP_VV_LOOP ({ - switch(STATE.VU.vsew){ + switch(p->VU.vsew){ case e32: vd = f32_add(vs1, vs2); break; diff --git a/riscv/insns/vfdiv_vf.h b/riscv/insns/vfdiv_vf.h index 356216c..50355c5 100644 --- a/riscv/insns/vfdiv_vf.h +++ b/riscv/insns/vfdiv_vf.h @@ -1,7 +1,7 @@ // vfdiv.vf vd, vs2, rs1 VFP_VF_LOOP ({ - switch(STATE.VU.vsew){ + switch(p->VU.vsew){ case e32: vd = f32_div(vs2, rs1); break; diff --git a/riscv/insns/vfdiv_vv.h b/riscv/insns/vfdiv_vv.h index a40deed..16769ea 100644 --- a/riscv/insns/vfdiv_vv.h +++ b/riscv/insns/vfdiv_vv.h @@ -1,7 +1,7 @@ // vfdiv.vv vd, vs2, vs1 VFP_VV_LOOP ({ - switch(STATE.VU.vsew){ + switch(p->VU.vsew){ case e32: vd = f32_div(vs2, vs1); break; diff --git a/riscv/insns/vfmacc_vf.h b/riscv/insns/vfmacc_vf.h index 94eaef5..4fc7272 100644 --- a/riscv/insns/vfmacc_vf.h +++ b/riscv/insns/vfmacc_vf.h @@ -1,7 +1,7 @@ // vfmacc.vf vd, rs1, vs2, vm # vd[i] = +(vs2[i] * x[rs1]) + vd[i] VFP_VF_LOOP ({ - switch(STATE.VU.vsew){ + switch(p->VU.vsew){ case e32: vd = f32_mulAdd(rs1, vs2, vd); break; diff --git a/riscv/insns/vfmacc_vv.h b/riscv/insns/vfmacc_vv.h index e819f75..eba6d09 100644 --- a/riscv/insns/vfmacc_vv.h +++ b/riscv/insns/vfmacc_vv.h @@ -1,7 +1,7 @@ // vfmacc.vv vd, rs1, vs2, vm # vd[i] = +(vs2[i] * vs1[i]) + vd[i] VFP_VV_LOOP ({ - switch(STATE.VU.vsew){ + switch(p->VU.vsew){ case e32: vd = f32_mulAdd(vs1, vs2, vd); break; diff --git a/riscv/insns/vfmadd_vf.h b/riscv/insns/vfmadd_vf.h index fd1291e..7a0aa06 100644 --- a/riscv/insns/vfmadd_vf.h +++ b/riscv/insns/vfmadd_vf.h @@ -1,7 +1,7 @@ // vfmadd: vd[i] = +(vd[i] * f[rs1]) + vs2[i] VFP_VF_LOOP ({ - switch(STATE.VU.vsew){ + switch(p->VU.vsew){ case e32: vd = f32_mulAdd(vd, rs1, vs2); break; diff --git a/riscv/insns/vfmadd_vv.h b/riscv/insns/vfmadd_vv.h index 15bace2..af58602 100644 --- a/riscv/insns/vfmadd_vv.h +++ b/riscv/insns/vfmadd_vv.h @@ -1,7 +1,7 @@ // vfmadd: vd[i] = +(vd[i] * vs1[i]) + vs2[i] VFP_VV_LOOP ({ - switch(STATE.VU.vsew){ + switch(p->VU.vsew){ case e32: vd = f32_mulAdd(vd, vs1, vs2); break; diff --git a/riscv/insns/vfmax_vf.h b/riscv/insns/vfmax_vf.h index caff350..a1f943c 100644 --- a/riscv/insns/vfmax_vf.h +++ b/riscv/insns/vfmax_vf.h @@ -1,7 +1,7 @@ // vfmax VFP_VF_LOOP ({ - switch(STATE.VU.vsew){ + switch(p->VU.vsew){ case e32: vd = f32_max(vs2, rs1); break; diff --git a/riscv/insns/vfmax_vv.h b/riscv/insns/vfmax_vv.h index 296ea01..e438678 100644 --- a/riscv/insns/vfmax_vv.h +++ b/riscv/insns/vfmax_vv.h @@ -1,7 +1,7 @@ // vfmax VFP_VV_LOOP ({ - switch(STATE.VU.vsew){ + switch(p->VU.vsew){ case e32: vd = f32_max(vs2, vs1); break; diff --git a/riscv/insns/vfmin_vf.h b/riscv/insns/vfmin_vf.h index e4f3a9c..b565f7b 100644 --- a/riscv/insns/vfmin_vf.h +++ b/riscv/insns/vfmin_vf.h @@ -1,7 +1,7 @@ // vfmin vd, vs2, rs1 VFP_VF_LOOP ({ - switch(STATE.VU.vsew){ + switch(p->VU.vsew){ case e32: vd = f32_min(vs2, rs1); break; diff --git a/riscv/insns/vfmin_vv.h b/riscv/insns/vfmin_vv.h index 8c9625f..d139bba 100644 --- a/riscv/insns/vfmin_vv.h +++ b/riscv/insns/vfmin_vv.h @@ -1,7 +1,7 @@ // vfmin vd, vs2, vs1 VFP_VV_LOOP ({ - switch(STATE.VU.vsew){ + switch(p->VU.vsew){ case e32: vd = f32_min(vs2, vs1); break; diff --git a/riscv/insns/vfmsac_vf.h b/riscv/insns/vfmsac_vf.h index b1c166f..e65d535 100644 --- a/riscv/insns/vfmsac_vf.h +++ b/riscv/insns/vfmsac_vf.h @@ -1,7 +1,7 @@ // vfmsac: vd[i] = +(f[rs1] * vs2[i]) - vd[i] VFP_VF_LOOP ({ - switch(STATE.VU.vsew){ + switch(p->VU.vsew){ case e32: vd = f32_mulAdd(rs1, vs2, f32(vd.v ^ F32_SIGN)); break; diff --git a/riscv/insns/vfmsac_vv.h b/riscv/insns/vfmsac_vv.h index 632d745..c719600 100644 --- a/riscv/insns/vfmsac_vv.h +++ b/riscv/insns/vfmsac_vv.h @@ -1,7 +1,7 @@ // vfmsac: vd[i] = +(vs1[i] * vs2[i]) - vd[i] VFP_VV_LOOP ({ - switch(STATE.VU.vsew){ + switch(p->VU.vsew){ case e32: vd = f32_mulAdd(vs1, vs2, f32(vd.v ^ F32_SIGN)); break; diff --git a/riscv/insns/vfmsub_vf.h b/riscv/insns/vfmsub_vf.h index a85d267..1794326 100644 --- a/riscv/insns/vfmsub_vf.h +++ b/riscv/insns/vfmsub_vf.h @@ -1,7 +1,7 @@ // vfmsub: vd[i] = +(vd[i] * f[rs1]) - vs2[i] VFP_VF_LOOP ({ - switch(STATE.VU.vsew){ + switch(p->VU.vsew){ case e32: vd = f32_mulAdd(vd, rs1, f32(vs2.v ^ F32_SIGN)); break; diff --git a/riscv/insns/vfmsub_vv.h b/riscv/insns/vfmsub_vv.h index a2ea57d..d75ff4c 100644 --- a/riscv/insns/vfmsub_vv.h +++ b/riscv/insns/vfmsub_vv.h @@ -1,7 +1,7 @@ // vfmsub: vd[i] = +(vd[i] * vs1[i]) - vs2[i] VFP_VV_LOOP ({ - switch(STATE.VU.vsew){ + switch(p->VU.vsew){ case e32: vd = f32_mulAdd(vd, vs1, f32(vs2.v ^ F32_SIGN)); break; diff --git a/riscv/insns/vfmul_vf.h b/riscv/insns/vfmul_vf.h index 8e74b68..0ce9660 100644 --- a/riscv/insns/vfmul_vf.h +++ b/riscv/insns/vfmul_vf.h @@ -2,7 +2,7 @@ require_fp; VFP_VF_LOOP ({ - switch(STATE.VU.vsew){ + switch(p->VU.vsew){ case e32: vd = f32_mul(rs1, vs2); break; diff --git a/riscv/insns/vfmul_vv.h b/riscv/insns/vfmul_vv.h index b9306c4..1bd9b3e 100644 --- a/riscv/insns/vfmul_vv.h +++ b/riscv/insns/vfmul_vv.h @@ -2,7 +2,7 @@ require_fp; VFP_VV_LOOP ({ - switch(STATE.VU.vsew){ + switch(p->VU.vsew){ case e32: vd = f32_mul(vs1, vs2); break; diff --git a/riscv/insns/vfmv_f_s.h b/riscv/insns/vfmv_f_s.h index 7e488e3..a6a3da8 100644 --- a/riscv/insns/vfmv_f_s.h +++ b/riscv/insns/vfmv_f_s.h @@ -1,22 +1,22 @@ // vfmv_f_s: rd = vs2[0] (rs1=0) require_fp; -require(STATE.VU.vsew == e8 || STATE.VU.vsew == e16 || STATE.VU.vsew == e32 || STATE.VU.vsew == e64); +require(p->VU.vsew == e8 || p->VU.vsew == e16 || p->VU.vsew == e32 || p->VU.vsew == e64); reg_t rs2_num = insn.rs2(); uint64_t vs2_0 = 0; -const reg_t sew = STATE.VU.vsew; +const reg_t sew = p->VU.vsew; switch(sew) { case e8: - vs2_0 = STATE.VU.elt<uint8_t>(rs2_num, 0); + vs2_0 = p->VU.elt<uint8_t>(rs2_num, 0); break; case e16: - vs2_0 = STATE.VU.elt<uint16_t>(rs2_num, 0); + vs2_0 = p->VU.elt<uint16_t>(rs2_num, 0); break; case e32: - vs2_0 = STATE.VU.elt<uint32_t>(rs2_num, 0); + vs2_0 = p->VU.elt<uint32_t>(rs2_num, 0); break; default: - vs2_0 = STATE.VU.elt<uint64_t>(rs2_num, 0); + vs2_0 = p->VU.elt<uint64_t>(rs2_num, 0); break; } diff --git a/riscv/insns/vfmv_s_f.h b/riscv/insns/vfmv_s_f.h index b978fc9..039d841 100644 --- a/riscv/insns/vfmv_s_f.h +++ b/riscv/insns/vfmv_s_f.h @@ -1,22 +1,22 @@ // vfmv_s_f: vd[0] = rs1 (vs2=0) require_fp; -require(STATE.VU.vsew == e32); -reg_t vl = STATE.VU.vl; +require(p->VU.vsew == e32); +reg_t vl = p->VU.vl; if (vl > 0) { reg_t rd_num = insn.rd(); - reg_t sew = STATE.VU.vsew; + reg_t sew = p->VU.vsew; if (FLEN == 64) - STATE.VU.elt<uint32_t>(rd_num, 0) = f64(FRS1).v; + p->VU.elt<uint32_t>(rd_num, 0) = f64(FRS1).v; else - STATE.VU.elt<uint32_t>(rd_num, 0) = f32(FRS1).v; + p->VU.elt<uint32_t>(rd_num, 0) = f32(FRS1).v; - const reg_t max_len = STATE.VU.VLEN / sew; + const reg_t max_len = p->VU.VLEN / sew; for (reg_t i = 1; i < max_len; ++i){ switch(sew) { case e32: - STATE.VU.elt<uint32_t>(rd_num, i) = 0; + p->VU.elt<uint32_t>(rd_num, i) = 0; break; default: require(false); diff --git a/riscv/insns/vfnmacc_vf.h b/riscv/insns/vfnmacc_vf.h index 22f078b..e835a3d 100644 --- a/riscv/insns/vfnmacc_vf.h +++ b/riscv/insns/vfnmacc_vf.h @@ -1,7 +1,7 @@ // vfnmacc: vd[i] = -(f[rs1] * vs2[i]) - vd[i] VFP_VF_LOOP ({ - switch(STATE.VU.vsew){ + switch(p->VU.vsew){ case e32: vd = f32_mulAdd(rs1, f32(vs2.v ^ F32_SIGN), f32(vd.v ^ F32_SIGN)); break; diff --git a/riscv/insns/vfnmacc_vv.h b/riscv/insns/vfnmacc_vv.h index ff080e8..7690d39 100644 --- a/riscv/insns/vfnmacc_vv.h +++ b/riscv/insns/vfnmacc_vv.h @@ -1,7 +1,7 @@ // vfnmacc: vd[i] = -(vs1[i] * vs2[i]) - vd[i] VFP_VV_LOOP ({ - switch(STATE.VU.vsew){ + switch(p->VU.vsew){ case e32: vd = f32_mulAdd(f32(vs2.v ^ F32_SIGN), vs1, f32(vd.v ^ F32_SIGN)); break; diff --git a/riscv/insns/vfnmadd_vf.h b/riscv/insns/vfnmadd_vf.h index cab3eab..59d2ad1 100644 --- a/riscv/insns/vfnmadd_vf.h +++ b/riscv/insns/vfnmadd_vf.h @@ -1,7 +1,7 @@ // vfnmadd: vd[i] = -(vd[i] * f[rs1]) - vs2[i] VFP_VF_LOOP ({ - switch(STATE.VU.vsew){ + switch(p->VU.vsew){ case e32: vd = f32_mulAdd(f32(vd.v ^ F32_SIGN), rs1, f32(vs2.v ^ F32_SIGN)); break; diff --git a/riscv/insns/vfnmadd_vv.h b/riscv/insns/vfnmadd_vv.h index 4c3b502..34aef81 100644 --- a/riscv/insns/vfnmadd_vv.h +++ b/riscv/insns/vfnmadd_vv.h @@ -1,7 +1,7 @@ // vfnmadd: vd[i] = -(vd[i] * vs1[i]) - vs2[i] VFP_VV_LOOP ({ - switch(STATE.VU.vsew){ + switch(p->VU.vsew){ case e32: vd = f32_mulAdd(f32(vd.v ^ F32_SIGN), vs1, f32(vs2.v ^ F32_SIGN)); break; diff --git a/riscv/insns/vfnmsac_vf.h b/riscv/insns/vfnmsac_vf.h index 48705e8..e04f2a3 100644 --- a/riscv/insns/vfnmsac_vf.h +++ b/riscv/insns/vfnmsac_vf.h @@ -1,7 +1,7 @@ // vfnmsac: vd[i] = -(f[rs1] * vs2[i]) + vd[i] VFP_VF_LOOP ({ - switch(STATE.VU.vsew){ + switch(p->VU.vsew){ case e32: vd = f32_mulAdd(rs1, f32(vs2.v ^ F32_SIGN), vd); break; diff --git a/riscv/insns/vfnmsac_vv.h b/riscv/insns/vfnmsac_vv.h index 82a158e..d1c43e4 100644 --- a/riscv/insns/vfnmsac_vv.h +++ b/riscv/insns/vfnmsac_vv.h @@ -1,7 +1,7 @@ // vfnmsac.vv vd, vs1, vs2, vm # vd[i] = -(vs2[i] * vs1[i]) + vd[i] VFP_VV_LOOP ({ - switch(STATE.VU.vsew){ + switch(p->VU.vsew){ case e32: vd = f32_mulAdd(f32(vs1.v ^ F32_SIGN), vs2, vd); break; diff --git a/riscv/insns/vfnmsub_vf.h b/riscv/insns/vfnmsub_vf.h index 5b65f7c..baffcba 100644 --- a/riscv/insns/vfnmsub_vf.h +++ b/riscv/insns/vfnmsub_vf.h @@ -1,7 +1,7 @@ // vfnmsub: vd[i] = -(vd[i] * f[rs1]) + vs2[i] VFP_VF_LOOP ({ - switch(STATE.VU.vsew){ + switch(p->VU.vsew){ case e32: vd = f32_mulAdd(f32(vd.v ^ F32_SIGN), rs1, vs2); break; diff --git a/riscv/insns/vfnmsub_vv.h b/riscv/insns/vfnmsub_vv.h index 876fcf2..20d5ca1 100644 --- a/riscv/insns/vfnmsub_vv.h +++ b/riscv/insns/vfnmsub_vv.h @@ -1,7 +1,7 @@ // vfnmsub: vd[i] = -(vd[i] * vs1[i]) + vs2[i] VFP_VV_LOOP ({ - switch(STATE.VU.vsew){ + switch(p->VU.vsew){ case e32: vd = f32_mulAdd(f32(vd.v ^ F32_SIGN), vs1, vs2); break; diff --git a/riscv/insns/vfsgnj_vf.h b/riscv/insns/vfsgnj_vf.h index eb4b849..e06286f 100644 --- a/riscv/insns/vfsgnj_vf.h +++ b/riscv/insns/vfsgnj_vf.h @@ -1,7 +1,7 @@ // vfsgnj VFP_VF_LOOP ({ - switch(STATE.VU.vsew){ + switch(p->VU.vsew){ case e32: vd = fsgnj32(rs1.v, vs2.v, false, false); break; diff --git a/riscv/insns/vfsgnj_vv.h b/riscv/insns/vfsgnj_vv.h index 0a5931a..8ada8dc 100644 --- a/riscv/insns/vfsgnj_vv.h +++ b/riscv/insns/vfsgnj_vv.h @@ -1,7 +1,7 @@ // vfsgnj VFP_VV_LOOP ({ - switch(STATE.VU.vsew) { + switch(p->VU.vsew) { case e32: vd = fsgnj32(vs1.v, vs2.v, false, false); break; diff --git a/riscv/insns/vfsgnjn_vf.h b/riscv/insns/vfsgnjn_vf.h index d90d019..fad5552 100644 --- a/riscv/insns/vfsgnjn_vf.h +++ b/riscv/insns/vfsgnjn_vf.h @@ -1,7 +1,7 @@ // vfsgnn VFP_VF_LOOP ({ - switch(STATE.VU.vsew){ + switch(p->VU.vsew){ case e32: vd = fsgnj32(rs1.v, vs2.v, true, false); break; diff --git a/riscv/insns/vfsgnjn_vv.h b/riscv/insns/vfsgnjn_vv.h index 2401b07..41d0576 100644 --- a/riscv/insns/vfsgnjn_vv.h +++ b/riscv/insns/vfsgnjn_vv.h @@ -1,7 +1,7 @@ // vfsgnn VFP_VV_LOOP ({ - switch(STATE.VU.vsew){ + switch(p->VU.vsew){ case e32: vd = fsgnj32(vs1.v, vs2.v, true, false); break; diff --git a/riscv/insns/vfsgnjx_vf.h b/riscv/insns/vfsgnjx_vf.h index 93e97bb..e1b98a2 100644 --- a/riscv/insns/vfsgnjx_vf.h +++ b/riscv/insns/vfsgnjx_vf.h @@ -1,7 +1,7 @@ // vfsgnx VFP_VF_LOOP ({ - switch(STATE.VU.vsew){ + switch(p->VU.vsew){ case e32: vd = fsgnj32(rs1.v, vs2.v, false, true); break; diff --git a/riscv/insns/vfsgnjx_vv.h b/riscv/insns/vfsgnjx_vv.h index 9939ca0..2a522f0 100644 --- a/riscv/insns/vfsgnjx_vv.h +++ b/riscv/insns/vfsgnjx_vv.h @@ -1,7 +1,7 @@ // vfsgnx VFP_VV_LOOP ({ - switch(STATE.VU.vsew){ + switch(p->VU.vsew){ case e32: vd = fsgnj32(vs1.v, vs2.v, false, true); break; diff --git a/riscv/insns/vfsub_vf.h b/riscv/insns/vfsub_vf.h index bc1c193..8ffde90 100644 --- a/riscv/insns/vfsub_vf.h +++ b/riscv/insns/vfsub_vf.h @@ -1,7 +1,7 @@ // vfsub.vf vd, vs2, rs1 VFP_VF_LOOP ({ - switch(STATE.VU.vsew){ + switch(p->VU.vsew){ case e32: vd = f32_sub(vs2, rs1); break; diff --git a/riscv/insns/vfsub_vv.h b/riscv/insns/vfsub_vv.h index 18858d0..8f7e42e 100644 --- a/riscv/insns/vfsub_vv.h +++ b/riscv/insns/vfsub_vv.h @@ -1,7 +1,7 @@ // vfsub.vv vd, vs2, vs1 VFP_VV_LOOP ({ - switch(STATE.VU.vsew){ + switch(p->VU.vsew){ case e32: vd = f32_sub(vs2, vs1); break; diff --git a/riscv/insns/vfunary0_vv.h b/riscv/insns/vfunary0_vv.h index 3c9f0e9..3a51e92 100644 --- a/riscv/insns/vfunary0_vv.h +++ b/riscv/insns/vfunary0_vv.h @@ -1,17 +1,17 @@ // VFUNARY0 encoding space VFP_VV_LOOP ({ - switch(STATE.VU.vsew){ + switch(p->VU.vsew){ case e32: if (rs1_num == VFUNARY0::VFCVT_XU_F_V) { - STATE.VU.elt<uint32_t>(rd_num, i) = f32_to_ui32(vs2, STATE.frm, true); + p->VU.elt<uint32_t>(rd_num, i) = f32_to_ui32(vs2, STATE.frm, true); } else if (rs1_num == VFUNARY0::VFCVT_X_F_V) { - STATE.VU.elt<int32_t>(rd_num, i) = f32_to_i32(vs2, STATE.frm, true); + p->VU.elt<int32_t>(rd_num, i) = f32_to_i32(vs2, STATE.frm, true); } else if (rs1_num == VFUNARY0::VFCVT_F_XU_V) { - auto vs2_u = STATE.VU.elt<uint32_t>(rs2_num, i); + auto vs2_u = p->VU.elt<uint32_t>(rs2_num, i); vd = ui32_to_f32(vs2_u); } else if (rs1_num == VFUNARY0::VFCVT_F_X_V) { - auto vs2_i = STATE.VU.elt<int32_t>(rs2_num, i); + auto vs2_i = p->VU.elt<int32_t>(rs2_num, i); vd = i32_to_f32(vs2_i); } else if (rs1_num == VFUNARY0::VFWCVT_XU_F_V) { } else if (rs1_num == VFUNARY0::VFWCVT_X_F_V) { diff --git a/riscv/insns/vfunary1_vv.h b/riscv/insns/vfunary1_vv.h index 4ffe90f..d04d328 100644 --- a/riscv/insns/vfunary1_vv.h +++ b/riscv/insns/vfunary1_vv.h @@ -1,7 +1,7 @@ // VFUNARY1 encoding space VFP_VV_LOOP ({ - switch(STATE.VU.vsew){ + switch(p->VU.vsew){ case e32: if (RS1 == VFUNARY1::VFSQRT_V){ vd = f32_sqrt(vs2); diff --git a/riscv/insns/vlb_v.h b/riscv/insns/vlb_v.h index 1cdeda8..587fdca 100644 --- a/riscv/insns/vlb_v.h +++ b/riscv/insns/vlb_v.h @@ -1,39 +1,39 @@ // vlb.v and vlseg[2-8]b.v -require(STATE.VU.vsew >= e8); +require(p->VU.vsew >= e8); reg_t nf = insn.v_nf() + 1; -require((nf >= 2 && STATE.VU.vlmul == 1) || nf == 1); -reg_t vl = STATE.VU.vl; +require((nf >= 2 && p->VU.vlmul == 1) || nf == 1); +reg_t vl = p->VU.vl; reg_t baseAddr = RS1; reg_t vd = insn.rd(); -for (reg_t i = STATE.VU.vstart; i < vl; ++i) { +for (reg_t i = p->VU.vstart; i < vl; ++i) { V_LOOP_ELEMENT_SKIP; for (reg_t fn = 0; fn < nf; ++fn) { int64_t val = MMU.load_int8(baseAddr + (i * nf + fn) * 1); - if (STATE.VU.vsew == e8) { - STATE.VU.elt<uint8_t>(vd + fn, i) = val; - } else if (STATE.VU.vsew == e16) { - STATE.VU.elt<uint16_t>(vd + fn, i) = val; - } else if (STATE.VU.vsew == e32) { - STATE.VU.elt<uint32_t>(vd + fn, i) = val; + if (p->VU.vsew == e8) { + p->VU.elt<uint8_t>(vd + fn, i) = val; + } else if (p->VU.vsew == e16) { + p->VU.elt<uint16_t>(vd + fn, i) = val; + } else if (p->VU.vsew == e32) { + p->VU.elt<uint32_t>(vd + fn, i) = val; } else { - STATE.VU.elt<uint64_t>(vd + fn, i) = val; + p->VU.elt<uint64_t>(vd + fn, i) = val; } } } //zero unfilled part -for (reg_t i = vl; i < STATE.VU.vlmax; ++i) { +for (reg_t i = vl; i < p->VU.vlmax; ++i) { for (reg_t fn = 0; fn < nf; ++fn) { - if (STATE.VU.vsew == e8) { - STATE.VU.elt<uint8_t>(vd + fn, i) = 0; - } else if (STATE.VU.vsew == e16) { - STATE.VU.elt<uint16_t>(vd + fn, i) = 0; - } else if (STATE.VU.vsew == e32) { - STATE.VU.elt<uint32_t>(vd + fn, i) = 0; + if (p->VU.vsew == e8) { + p->VU.elt<uint8_t>(vd + fn, i) = 0; + } else if (p->VU.vsew == e16) { + p->VU.elt<uint16_t>(vd + fn, i) = 0; + } else if (p->VU.vsew == e32) { + p->VU.elt<uint32_t>(vd + fn, i) = 0; } else { - STATE.VU.elt<uint64_t>(vd + fn, i) = 0; + p->VU.elt<uint64_t>(vd + fn, i) = 0; } } } -STATE.VU.vstart = 0; +p->VU.vstart = 0; diff --git a/riscv/insns/vlbu_v.h b/riscv/insns/vlbu_v.h index 0d0d53a..54b7ea2 100644 --- a/riscv/insns/vlbu_v.h +++ b/riscv/insns/vlbu_v.h @@ -1,39 +1,39 @@ // vlbu.v and vlseg[2-8]bu.v -require(STATE.VU.vsew >= e8); +require(p->VU.vsew >= e8); reg_t nf = insn.v_nf() + 1; -require((nf >= 2 && STATE.VU.vlmul == 1) || nf == 1); -reg_t vl = STATE.VU.vl; +require((nf >= 2 && p->VU.vlmul == 1) || nf == 1); +reg_t vl = p->VU.vl; reg_t baseAddr = RS1; reg_t vd = insn.rd(); -for (reg_t i = STATE.VU.vstart; i < vl; ++i) { +for (reg_t i = p->VU.vstart; i < vl; ++i) { V_LOOP_ELEMENT_SKIP; for (reg_t fn = 0; fn < nf; ++fn) { uint64_t val = MMU.load_uint8(baseAddr + (i * nf + fn) * 1); - if (STATE.VU.vsew == e8) { - STATE.VU.elt<uint8_t>(vd + fn, i) = val; - } else if (STATE.VU.vsew == e16) { - STATE.VU.elt<uint16_t>(vd + fn, i) = val; - } else if (STATE.VU.vsew == e32) { - STATE.VU.elt<uint32_t>(vd + fn, i) = val; + if (p->VU.vsew == e8) { + p->VU.elt<uint8_t>(vd + fn, i) = val; + } else if (p->VU.vsew == e16) { + p->VU.elt<uint16_t>(vd + fn, i) = val; + } else if (p->VU.vsew == e32) { + p->VU.elt<uint32_t>(vd + fn, i) = val; } else { - STATE.VU.elt<uint64_t>(vd + fn, i) = val; + p->VU.elt<uint64_t>(vd + fn, i) = val; } } } //zero unfilled part -for (reg_t i = vl; i < STATE.VU.vlmax; ++i) { +for (reg_t i = vl; i < p->VU.vlmax; ++i) { for (reg_t fn = 0; fn < nf; ++fn) { - if (STATE.VU.vsew == e8) { - STATE.VU.elt<uint8_t>(vd + fn, i) = 0; - } else if (STATE.VU.vsew == e16) { - STATE.VU.elt<uint16_t>(vd + fn, i) = 0; - } else if (STATE.VU.vsew == e32) { - STATE.VU.elt<uint32_t>(vd + fn, i) = 0; + if (p->VU.vsew == e8) { + p->VU.elt<uint8_t>(vd + fn, i) = 0; + } else if (p->VU.vsew == e16) { + p->VU.elt<uint16_t>(vd + fn, i) = 0; + } else if (p->VU.vsew == e32) { + p->VU.elt<uint32_t>(vd + fn, i) = 0; } else { - STATE.VU.elt<uint64_t>(vd + fn, i) = 0; + p->VU.elt<uint64_t>(vd + fn, i) = 0; } } } -STATE.VU.vstart = 0; +p->VU.vstart = 0; diff --git a/riscv/insns/vlh_v.h b/riscv/insns/vlh_v.h index ee572e7..d5ff723 100644 --- a/riscv/insns/vlh_v.h +++ b/riscv/insns/vlh_v.h @@ -1,35 +1,35 @@ // vlh.v and vlseg[2-8]h.v -require(STATE.VU.vsew >= e16); +require(p->VU.vsew >= e16); reg_t nf = insn.v_nf() + 1; -require((nf >= 2 && STATE.VU.vlmul == 1) || nf == 1); -reg_t vl = STATE.VU.vl; +require((nf >= 2 && p->VU.vlmul == 1) || nf == 1); +reg_t vl = p->VU.vl; reg_t baseAddr = RS1; reg_t vd = insn.rd(); -for (reg_t i=STATE.VU.vstart; i<vl; ++i) { +for (reg_t i=p->VU.vstart; i<vl; ++i) { V_LOOP_ELEMENT_SKIP; for (reg_t fn=0; fn<nf; ++fn) { int64_t val = MMU.load_int16(baseAddr + (i * nf + fn) * 2); - if (STATE.VU.vsew == e16) { - STATE.VU.elt<uint16_t>(vd+fn, i) = val; - } else if (STATE.VU.vsew == e32) { - STATE.VU.elt<uint32_t>(vd+fn, i) = val; + if (p->VU.vsew == e16) { + p->VU.elt<uint16_t>(vd+fn, i) = val; + } else if (p->VU.vsew == e32) { + p->VU.elt<uint32_t>(vd+fn, i) = val; } else { - STATE.VU.elt<uint64_t>(vd+fn, i) = val; + p->VU.elt<uint64_t>(vd+fn, i) = val; } } } //zero unfilled part -for (reg_t i=vl; i < STATE.VU.vlmax; ++i) { +for (reg_t i=vl; i < p->VU.vlmax; ++i) { for (reg_t fn=0; fn<nf; ++fn) { - if (STATE.VU.vsew == e16) { - STATE.VU.elt<uint16_t>(vd+fn, i) = 0; - } else if (STATE.VU.vsew == e32) { - STATE.VU.elt<uint32_t>(vd+fn, i) = 0; + if (p->VU.vsew == e16) { + p->VU.elt<uint16_t>(vd+fn, i) = 0; + } else if (p->VU.vsew == e32) { + p->VU.elt<uint32_t>(vd+fn, i) = 0; } else { - STATE.VU.elt<uint64_t>(vd+fn, i) = 0; + p->VU.elt<uint64_t>(vd+fn, i) = 0; } } } -STATE.VU.vstart = 0; +p->VU.vstart = 0; diff --git a/riscv/insns/vlhu_v.h b/riscv/insns/vlhu_v.h index d7559d4..9eab965 100644 --- a/riscv/insns/vlhu_v.h +++ b/riscv/insns/vlhu_v.h @@ -1,35 +1,35 @@ // vlhu.v and vlseg[2-8]hu.v -require(STATE.VU.vsew >= e16); +require(p->VU.vsew >= e16); reg_t nf = insn.v_nf() + 1; -require((nf >= 2 && STATE.VU.vlmul == 1) || nf == 1); -reg_t vl = STATE.VU.vl; +require((nf >= 2 && p->VU.vlmul == 1) || nf == 1); +reg_t vl = p->VU.vl; reg_t baseAddr = RS1; reg_t vd = insn.rd(); -for (reg_t i = STATE.VU.vstart; i < vl; ++i) { +for (reg_t i = p->VU.vstart; i < vl; ++i) { V_LOOP_ELEMENT_SKIP; for (reg_t fn = 0; fn < nf; ++fn) { uint64_t val = MMU.load_uint16(baseAddr + (i * nf + fn) * 2); - if (STATE.VU.vsew == e16) { - STATE.VU.elt<uint16_t>(vd + fn, i) = val; - } else if (STATE.VU.vsew == e32) { - STATE.VU.elt<uint32_t>(vd + fn, i) = val; + if (p->VU.vsew == e16) { + p->VU.elt<uint16_t>(vd + fn, i) = val; + } else if (p->VU.vsew == e32) { + p->VU.elt<uint32_t>(vd + fn, i) = val; } else { - STATE.VU.elt<uint64_t>(vd + fn, i) = val; + p->VU.elt<uint64_t>(vd + fn, i) = val; } } } //zero unfilled part -for (reg_t i = vl; i < STATE.VU.vlmax; ++i) { +for (reg_t i = vl; i < p->VU.vlmax; ++i) { for (reg_t fn = 0; fn < nf; ++fn) { - if (STATE.VU.vsew == e16) { - STATE.VU.elt<uint16_t>(vd + fn, i) = 0; - } else if (STATE.VU.vsew == e32) { - STATE.VU.elt<uint32_t>(vd + fn, i) = 0; + if (p->VU.vsew == e16) { + p->VU.elt<uint16_t>(vd + fn, i) = 0; + } else if (p->VU.vsew == e32) { + p->VU.elt<uint32_t>(vd + fn, i) = 0; } else { - STATE.VU.elt<uint64_t>(vd + fn, i) = 0; + p->VU.elt<uint64_t>(vd + fn, i) = 0; } } } -STATE.VU.vstart = 0; +p->VU.vstart = 0; diff --git a/riscv/insns/vlsb_v.h b/riscv/insns/vlsb_v.h index 637640a..4e67339 100644 --- a/riscv/insns/vlsb_v.h +++ b/riscv/insns/vlsb_v.h @@ -1,40 +1,40 @@ // vlsb.v and vlsseg[2-8]b.v -require(STATE.VU.vsew >= e8); +require(p->VU.vsew >= e8); reg_t nf = insn.v_nf() + 1; -require((nf >= 2 && STATE.VU.vlmul == 1) || nf == 1); -reg_t vl = STATE.VU.vl; +require((nf >= 2 && p->VU.vlmul == 1) || nf == 1); +reg_t vl = p->VU.vl; reg_t baseAddr = RS1; reg_t stride = RS2; reg_t vd = insn.rd(); -for (reg_t i = STATE.VU.vstart; i < vl; ++i) { +for (reg_t i = p->VU.vstart; i < vl; ++i) { V_LOOP_ELEMENT_SKIP; for (reg_t fn = 0; fn < nf; ++fn) { int64_t val = MMU.load_int8(baseAddr + i * stride + fn * 1); - if (STATE.VU.vsew == e8) { - STATE.VU.elt<uint8_t>(vd + fn, i) = val; - } else if (STATE.VU.vsew == e16) { - STATE.VU.elt<uint16_t>(vd + fn, i) = val; - } else if (STATE.VU.vsew == e32) { - STATE.VU.elt<uint32_t>(vd + fn, i) = val; + if (p->VU.vsew == e8) { + p->VU.elt<uint8_t>(vd + fn, i) = val; + } else if (p->VU.vsew == e16) { + p->VU.elt<uint16_t>(vd + fn, i) = val; + } else if (p->VU.vsew == e32) { + p->VU.elt<uint32_t>(vd + fn, i) = val; } else { - STATE.VU.elt<uint64_t>(vd + fn, i) = val; + p->VU.elt<uint64_t>(vd + fn, i) = val; } } } //zero unfilled part -for (reg_t i = vl; i < STATE.VU.vlmax; ++i) { +for (reg_t i = vl; i < p->VU.vlmax; ++i) { for (reg_t fn = 0; fn < nf; ++fn) { - if (STATE.VU.vsew == e8) { - STATE.VU.elt<uint8_t>(vd + fn, i) = 0; - } else if (STATE.VU.vsew == e16) { - STATE.VU.elt<uint16_t>(vd + fn, i) = 0; - } else if (STATE.VU.vsew == e32) { - STATE.VU.elt<uint32_t>(vd + fn, i) = 0; + if (p->VU.vsew == e8) { + p->VU.elt<uint8_t>(vd + fn, i) = 0; + } else if (p->VU.vsew == e16) { + p->VU.elt<uint16_t>(vd + fn, i) = 0; + } else if (p->VU.vsew == e32) { + p->VU.elt<uint32_t>(vd + fn, i) = 0; } else { - STATE.VU.elt<uint64_t>(vd + fn, i) = 0; + p->VU.elt<uint64_t>(vd + fn, i) = 0; } } } -STATE.VU.vstart = 0; +p->VU.vstart = 0; diff --git a/riscv/insns/vlsbu_v.h b/riscv/insns/vlsbu_v.h index 38371a9..2a85fae 100644 --- a/riscv/insns/vlsbu_v.h +++ b/riscv/insns/vlsbu_v.h @@ -1,40 +1,40 @@ // vlsb.v and vlsseg[2-8]b.v -require(STATE.VU.vsew >= e8); +require(p->VU.vsew >= e8); reg_t nf = insn.v_nf() + 1; -require((nf >= 2 && STATE.VU.vlmul == 1) || nf == 1); -reg_t vl = STATE.VU.vl; +require((nf >= 2 && p->VU.vlmul == 1) || nf == 1); +reg_t vl = p->VU.vl; reg_t baseAddr = RS1; reg_t stride = RS2; reg_t vd = insn.rd(); -for (reg_t i = STATE.VU.vstart; i < vl; ++i) { +for (reg_t i = p->VU.vstart; i < vl; ++i) { V_LOOP_ELEMENT_SKIP; for (reg_t fn = 0; fn < nf; ++fn) { uint64_t val = MMU.load_int8(baseAddr + i * stride + fn * 1); - if (STATE.VU.vsew == e8) { - STATE.VU.elt<uint8_t>(vd + fn, i) = val; - } else if (STATE.VU.vsew == e16) { - STATE.VU.elt<uint16_t>(vd + fn, i) = val; - } else if (STATE.VU.vsew == e32) { - STATE.VU.elt<uint32_t>(vd + fn, i) = val; + if (p->VU.vsew == e8) { + p->VU.elt<uint8_t>(vd + fn, i) = val; + } else if (p->VU.vsew == e16) { + p->VU.elt<uint16_t>(vd + fn, i) = val; + } else if (p->VU.vsew == e32) { + p->VU.elt<uint32_t>(vd + fn, i) = val; } else { - STATE.VU.elt<uint64_t>(vd + fn, i) = val; + p->VU.elt<uint64_t>(vd + fn, i) = val; } } } //zero unfilled part -for (reg_t i = vl; i < STATE.VU.vlmax; ++i) { +for (reg_t i = vl; i < p->VU.vlmax; ++i) { for (reg_t fn = 0; fn < nf; ++fn) { - if (STATE.VU.vsew == e8) { - STATE.VU.elt<uint8_t>(vd + fn, i) = 0; - } else if (STATE.VU.vsew == e16) { - STATE.VU.elt<uint16_t>(vd + fn, i) = 0; - } else if (STATE.VU.vsew == e32) { - STATE.VU.elt<uint32_t>(vd + fn, i) = 0; + if (p->VU.vsew == e8) { + p->VU.elt<uint8_t>(vd + fn, i) = 0; + } else if (p->VU.vsew == e16) { + p->VU.elt<uint16_t>(vd + fn, i) = 0; + } else if (p->VU.vsew == e32) { + p->VU.elt<uint32_t>(vd + fn, i) = 0; } else { - STATE.VU.elt<uint64_t>(vd + fn, i) = 0; + p->VU.elt<uint64_t>(vd + fn, i) = 0; } } } -STATE.VU.vstart = 0; +p->VU.vstart = 0; diff --git a/riscv/insns/vlsh_v.h b/riscv/insns/vlsh_v.h index b4a770c..4c896d5 100644 --- a/riscv/insns/vlsh_v.h +++ b/riscv/insns/vlsh_v.h @@ -1,36 +1,36 @@ // vlsh.v and vlsseg[2-8]h.v -require(STATE.VU.vsew >= e16); +require(p->VU.vsew >= e16); reg_t nf = insn.v_nf() + 1; -require((nf >= 2 && STATE.VU.vlmul == 1) || nf == 1); -reg_t vl = STATE.VU.vl; +require((nf >= 2 && p->VU.vlmul == 1) || nf == 1); +reg_t vl = p->VU.vl; reg_t baseAddr = RS1; reg_t stride = RS2; reg_t vd = insn.rd(); -for (reg_t i = STATE.VU.vstart; i < vl; ++i) { +for (reg_t i = p->VU.vstart; i < vl; ++i) { V_LOOP_ELEMENT_SKIP; for (reg_t fn = 0; fn < nf; ++fn) { int64_t val = MMU.load_int16(baseAddr + i * stride + fn * 2); - if (STATE.VU.vsew == e16) { - STATE.VU.elt<uint16_t>(vd + fn, i) = val; - } else if (STATE.VU.vsew == e32) { - STATE.VU.elt<uint32_t>(vd + fn, i) = val; + if (p->VU.vsew == e16) { + p->VU.elt<uint16_t>(vd + fn, i) = val; + } else if (p->VU.vsew == e32) { + p->VU.elt<uint32_t>(vd + fn, i) = val; } else { - STATE.VU.elt<uint64_t>(vd + fn, i) = val; + p->VU.elt<uint64_t>(vd + fn, i) = val; } } } //zero unfilled part -for (reg_t i = vl; i < STATE.VU.vlmax; ++i) { +for (reg_t i = vl; i < p->VU.vlmax; ++i) { for (reg_t fn = 0; fn < nf; ++fn) { - if (STATE.VU.vsew == e16) { - STATE.VU.elt<uint16_t>(vd + fn, i) = 0; - } else if (STATE.VU.vsew == e32) { - STATE.VU.elt<uint32_t>(vd + fn, i) = 0; + if (p->VU.vsew == e16) { + p->VU.elt<uint16_t>(vd + fn, i) = 0; + } else if (p->VU.vsew == e32) { + p->VU.elt<uint32_t>(vd + fn, i) = 0; } else { - STATE.VU.elt<uint64_t>(vd + fn, i) = 0; + p->VU.elt<uint64_t>(vd + fn, i) = 0; } } } -STATE.VU.vstart = 0; +p->VU.vstart = 0; diff --git a/riscv/insns/vlshu_v.h b/riscv/insns/vlshu_v.h index e2d2821..bdc7880 100644 --- a/riscv/insns/vlshu_v.h +++ b/riscv/insns/vlshu_v.h @@ -1,36 +1,36 @@ // vlsh.v and vlsseg[2-8]h.v -require(STATE.VU.vsew >= e16); +require(p->VU.vsew >= e16); reg_t nf = insn.v_nf() + 1; -require((nf >= 2 && STATE.VU.vlmul == 1) || nf == 1); -reg_t vl = STATE.VU.vl; +require((nf >= 2 && p->VU.vlmul == 1) || nf == 1); +reg_t vl = p->VU.vl; reg_t baseAddr = RS1; reg_t stride = RS2; reg_t vd = insn.rd(); -for (reg_t i = STATE.VU.vstart; i < vl; ++i) { +for (reg_t i = p->VU.vstart; i < vl; ++i) { V_LOOP_ELEMENT_SKIP; for (reg_t fn = 0; fn < nf; ++fn) { uint64_t val = MMU.load_int16(baseAddr + i * stride + fn * 2); - if (STATE.VU.vsew == e16) { - STATE.VU.elt<uint16_t>(vd + fn, i) = val; - } else if (STATE.VU.vsew == e32) { - STATE.VU.elt<uint32_t>(vd + fn, i) = val; + if (p->VU.vsew == e16) { + p->VU.elt<uint16_t>(vd + fn, i) = val; + } else if (p->VU.vsew == e32) { + p->VU.elt<uint32_t>(vd + fn, i) = val; } else { - STATE.VU.elt<uint64_t>(vd + fn, i) = val; + p->VU.elt<uint64_t>(vd + fn, i) = val; } } } //zero unfilled part -for (reg_t i = vl; i < STATE.VU.vlmax; ++i) { +for (reg_t i = vl; i < p->VU.vlmax; ++i) { for (reg_t fn = 0; fn < nf; ++fn) { - if (STATE.VU.vsew == e16) { - STATE.VU.elt<uint16_t>(vd + fn, i) = 0; - } else if (STATE.VU.vsew == e32) { - STATE.VU.elt<uint32_t>(vd + fn, i) = 0; + if (p->VU.vsew == e16) { + p->VU.elt<uint16_t>(vd + fn, i) = 0; + } else if (p->VU.vsew == e32) { + p->VU.elt<uint32_t>(vd + fn, i) = 0; } else { - STATE.VU.elt<uint64_t>(vd + fn, i) = 0; + p->VU.elt<uint64_t>(vd + fn, i) = 0; } } } -STATE.VU.vstart = 0; +p->VU.vstart = 0; diff --git a/riscv/insns/vlsw_v.h b/riscv/insns/vlsw_v.h index 769e27b..468d20a 100644 --- a/riscv/insns/vlsw_v.h +++ b/riscv/insns/vlsw_v.h @@ -1,32 +1,32 @@ // vlsw.v and vlsseg[2-8]w.v -require(STATE.VU.vsew >= e32); +require(p->VU.vsew >= e32); reg_t nf = insn.v_nf() + 1; -require((nf >= 2 && STATE.VU.vlmul == 1) || nf == 1); -reg_t vl = STATE.VU.vl; +require((nf >= 2 && p->VU.vlmul == 1) || nf == 1); +reg_t vl = p->VU.vl; reg_t baseAddr = RS1; reg_t stride = RS2; reg_t vd = insn.rd(); -for (reg_t i = STATE.VU.vstart; i < vl; ++i) { +for (reg_t i = p->VU.vstart; i < vl; ++i) { V_LOOP_ELEMENT_SKIP; for (reg_t fn = 0; fn < nf; ++fn) { int64_t val = MMU.load_int32(baseAddr + i * stride + fn * 4); - if (STATE.VU.vsew == e32) { - STATE.VU.elt<uint32_t>(vd + fn, i) = val; + if (p->VU.vsew == e32) { + p->VU.elt<uint32_t>(vd + fn, i) = val; } else { - STATE.VU.elt<uint64_t>(vd + fn, i) = val; + p->VU.elt<uint64_t>(vd + fn, i) = val; } } } //zero unfilled part -for (reg_t i = vl; i < STATE.VU.vlmax; ++i) { +for (reg_t i = vl; i < p->VU.vlmax; ++i) { for (reg_t fn = 0; fn < nf; ++fn) { - if (STATE.VU.vsew == e32) { - STATE.VU.elt<uint32_t>(vd + fn, i) = 0; + if (p->VU.vsew == e32) { + p->VU.elt<uint32_t>(vd + fn, i) = 0; } else { - STATE.VU.elt<uint64_t>(vd + fn, i) = 0; + p->VU.elt<uint64_t>(vd + fn, i) = 0; } } } -STATE.VU.vstart = 0; +p->VU.vstart = 0; diff --git a/riscv/insns/vlswu_v.h b/riscv/insns/vlswu_v.h index 0bc00dc..7e0c6a2 100644 --- a/riscv/insns/vlswu_v.h +++ b/riscv/insns/vlswu_v.h @@ -1,32 +1,32 @@ // vlsw.v and vlsseg[2-8]w.v -require(STATE.VU.vsew >= e32); +require(p->VU.vsew >= e32); reg_t nf = insn.v_nf() + 1; -require((nf >= 2 && STATE.VU.vlmul == 1) || nf == 1); -reg_t vl = STATE.VU.vl; +require((nf >= 2 && p->VU.vlmul == 1) || nf == 1); +reg_t vl = p->VU.vl; reg_t baseAddr = RS1; reg_t stride = RS2; reg_t vd = insn.rd(); -for (reg_t i = STATE.VU.vstart; i < vl; ++i) { +for (reg_t i = p->VU.vstart; i < vl; ++i) { V_LOOP_ELEMENT_SKIP; for (reg_t fn = 0; fn < nf; ++fn) { uint64_t val = MMU.load_int32(baseAddr + i * stride + fn * 4); - if (STATE.VU.vsew == e32) { - STATE.VU.elt<uint32_t>(vd + fn, i) = val; + if (p->VU.vsew == e32) { + p->VU.elt<uint32_t>(vd + fn, i) = val; } else { - STATE.VU.elt<uint64_t>(vd + fn, i) = val; + p->VU.elt<uint64_t>(vd + fn, i) = val; } } } //zero unfilled part -for (reg_t i = vl; i < STATE.VU.vlmax; ++i) { +for (reg_t i = vl; i < p->VU.vlmax; ++i) { for (reg_t fn = 0; fn < nf; ++fn) { - if (STATE.VU.vsew == e32) { - STATE.VU.elt<uint32_t>(vd + fn, i) = 0; + if (p->VU.vsew == e32) { + p->VU.elt<uint32_t>(vd + fn, i) = 0; } else { - STATE.VU.elt<uint64_t>(vd + fn, i) = 0; + p->VU.elt<uint64_t>(vd + fn, i) = 0; } } } -STATE.VU.vstart = 0; +p->VU.vstart = 0; diff --git a/riscv/insns/vlw_v.h b/riscv/insns/vlw_v.h index dccf3e9..d1a546f 100644 --- a/riscv/insns/vlw_v.h +++ b/riscv/insns/vlw_v.h @@ -1,31 +1,31 @@ // vlw.v and vlseg[2-8]w.v -require(STATE.VU.vsew >= e32); +require(p->VU.vsew >= e32); reg_t nf = insn.v_nf() + 1; -require((nf >= 2 && STATE.VU.vlmul == 1) || nf == 1); -reg_t vl = STATE.VU.vl; +require((nf >= 2 && p->VU.vlmul == 1) || nf == 1); +reg_t vl = p->VU.vl; reg_t baseAddr = RS1; reg_t vd = insn.rd(); -for (reg_t i = STATE.VU.vstart; i < vl; ++i) { +for (reg_t i = p->VU.vstart; i < vl; ++i) { V_LOOP_ELEMENT_SKIP; for (reg_t fn = 0; fn < nf; ++fn) { int64_t val = MMU.load_int32(baseAddr + (i * nf + fn) * 4); - if (STATE.VU.vsew == e32) { - STATE.VU.elt<uint32_t>(vd + fn, i) = val; + if (p->VU.vsew == e32) { + p->VU.elt<uint32_t>(vd + fn, i) = val; } else { - STATE.VU.elt<uint64_t>(vd + fn, i) = val; + p->VU.elt<uint64_t>(vd + fn, i) = val; } } } //zero unfilled part -for (reg_t i = vl; i < STATE.VU.vlmax; ++i) { +for (reg_t i = vl; i < p->VU.vlmax; ++i) { for (reg_t fn = 0; fn < nf; ++fn) { - if (STATE.VU.vsew == e32) { - STATE.VU.elt<uint32_t>(vd + fn, i) = 0; + if (p->VU.vsew == e32) { + p->VU.elt<uint32_t>(vd + fn, i) = 0; } else { - STATE.VU.elt<uint64_t>(vd + fn, i) = 0; + p->VU.elt<uint64_t>(vd + fn, i) = 0; } } } -STATE.VU.vstart = 0; +p->VU.vstart = 0; diff --git a/riscv/insns/vlwu_v.h b/riscv/insns/vlwu_v.h index 676b44f..2702459 100644 --- a/riscv/insns/vlwu_v.h +++ b/riscv/insns/vlwu_v.h @@ -1,31 +1,31 @@ // vlwu.v and vlseg[2-8]wu.v -require(STATE.VU.vsew >= e32); +require(p->VU.vsew >= e32); reg_t nf = insn.v_nf() + 1; -require((nf >= 2 && STATE.VU.vlmul == 1) || nf == 1); -reg_t vl = STATE.VU.vl; +require((nf >= 2 && p->VU.vlmul == 1) || nf == 1); +reg_t vl = p->VU.vl; reg_t baseAddr = RS1; reg_t vd = insn.rd(); -for (reg_t i = STATE.VU.vstart; i < vl; ++i) { +for (reg_t i = p->VU.vstart; i < vl; ++i) { V_LOOP_ELEMENT_SKIP; for (reg_t fn = 0; fn < nf; ++fn) { uint64_t val = MMU.load_uint32(baseAddr + (i * nf + fn) * 4); - if (STATE.VU.vsew == e32) { - STATE.VU.elt<uint32_t>(vd + fn, i) = val; + if (p->VU.vsew == e32) { + p->VU.elt<uint32_t>(vd + fn, i) = val; } else { - STATE.VU.elt<uint64_t>(vd + fn, i) = val; + p->VU.elt<uint64_t>(vd + fn, i) = val; } } } //zero unfilled part -for (reg_t i = vl; i < STATE.VU.vlmax; ++i) { +for (reg_t i = vl; i < p->VU.vlmax; ++i) { for (reg_t fn = 0; fn < nf; ++fn) { - if (STATE.VU.vsew == e32) { - STATE.VU.elt<uint32_t>(vd + fn, i) = 0; + if (p->VU.vsew == e32) { + p->VU.elt<uint32_t>(vd + fn, i) = 0; } else { - STATE.VU.elt<uint64_t>(vd + fn, i) = 0; + p->VU.elt<uint64_t>(vd + fn, i) = 0; } } } -STATE.VU.vstart = 0; +p->VU.vstart = 0; diff --git a/riscv/insns/vlxb_v.h b/riscv/insns/vlxb_v.h index 5504fcf..370bec7 100644 --- a/riscv/insns/vlxb_v.h +++ b/riscv/insns/vlxb_v.h @@ -1,41 +1,41 @@ // vlxb.v and vlsseg[2-8]b.v -require(STATE.VU.vsew >= e8); +require(p->VU.vsew >= e8); reg_t nf = insn.v_nf() + 1; -require((nf >= 2 && STATE.VU.vlmul == 1) || nf == 1); -reg_t vl = STATE.VU.vl; +require((nf >= 2 && p->VU.vlmul == 1) || nf == 1); +reg_t vl = p->VU.vl; reg_t baseAddr = RS1; reg_t stride = insn.rs2(); reg_t vd = insn.rd(); -for (reg_t i = STATE.VU.vstart; i < vl; ++i) { +for (reg_t i = p->VU.vstart; i < vl; ++i) { V_LOOP_ELEMENT_SKIP; - reg_t index = STATE.VU.elt<int8_t>(stride, i); + reg_t index = p->VU.elt<int8_t>(stride, i); for (reg_t fn = 0; fn < nf; ++fn) { int64_t val = MMU.load_int8(baseAddr + index + fn * 1); - if (STATE.VU.vsew == e8) { - STATE.VU.elt<uint8_t>(vd + fn, i) = val; - } else if (STATE.VU.vsew == e16) { - STATE.VU.elt<uint16_t>(vd + fn, i) = val; - } else if (STATE.VU.vsew == e32) { - STATE.VU.elt<uint32_t>(vd + fn, i) = val; + if (p->VU.vsew == e8) { + p->VU.elt<uint8_t>(vd + fn, i) = val; + } else if (p->VU.vsew == e16) { + p->VU.elt<uint16_t>(vd + fn, i) = val; + } else if (p->VU.vsew == e32) { + p->VU.elt<uint32_t>(vd + fn, i) = val; } else { - STATE.VU.elt<uint64_t>(vd + fn, i) = val; + p->VU.elt<uint64_t>(vd + fn, i) = val; } } } //zero unfilled part -for (reg_t i = vl; i < STATE.VU.vlmax; ++i) { +for (reg_t i = vl; i < p->VU.vlmax; ++i) { for (reg_t fn = 0; fn < nf; ++fn) { - if (STATE.VU.vsew == e8) { - STATE.VU.elt<uint8_t>(vd + fn, i) = 0; - } else if (STATE.VU.vsew == e16) { - STATE.VU.elt<uint16_t>(vd + fn, i) = 0; - } else if (STATE.VU.vsew == e32) { - STATE.VU.elt<uint32_t>(vd + fn, i) = 0; + if (p->VU.vsew == e8) { + p->VU.elt<uint8_t>(vd + fn, i) = 0; + } else if (p->VU.vsew == e16) { + p->VU.elt<uint16_t>(vd + fn, i) = 0; + } else if (p->VU.vsew == e32) { + p->VU.elt<uint32_t>(vd + fn, i) = 0; } else { - STATE.VU.elt<uint64_t>(vd + fn, i) = 0; + p->VU.elt<uint64_t>(vd + fn, i) = 0; } } } -STATE.VU.vstart = 0; +p->VU.vstart = 0; diff --git a/riscv/insns/vlxbu_v.h b/riscv/insns/vlxbu_v.h index f747883..9372bdb 100644 --- a/riscv/insns/vlxbu_v.h +++ b/riscv/insns/vlxbu_v.h @@ -1,41 +1,41 @@ // vlxbu.v and vlxseg[2-8]bu.v -require(STATE.VU.vsew >= e8); +require(p->VU.vsew >= e8); reg_t nf = insn.v_nf() + 1; -require((nf >= 2 && STATE.VU.vlmul == 1) || nf == 1); -reg_t vl = STATE.VU.vl; +require((nf >= 2 && p->VU.vlmul == 1) || nf == 1); +reg_t vl = p->VU.vl; reg_t baseAddr = RS1; reg_t stride = insn.rs2(); reg_t vd = insn.rd(); -for (reg_t i = STATE.VU.vstart; i < vl; ++i) { +for (reg_t i = p->VU.vstart; i < vl; ++i) { V_LOOP_ELEMENT_SKIP; - reg_t index = STATE.VU.elt<int8_t>(stride, i); + reg_t index = p->VU.elt<int8_t>(stride, i); for (reg_t fn = 0; fn < nf; ++fn) { uint64_t val = MMU.load_uint8(baseAddr + index + fn * 1); - if (STATE.VU.vsew == e8) { - STATE.VU.elt<uint8_t>(vd + fn, i) = val; - } else if (STATE.VU.vsew == e16) { - STATE.VU.elt<uint16_t>(vd + fn, i) = val; - } else if (STATE.VU.vsew == e32) { - STATE.VU.elt<uint32_t>(vd + fn, i) = val; + if (p->VU.vsew == e8) { + p->VU.elt<uint8_t>(vd + fn, i) = val; + } else if (p->VU.vsew == e16) { + p->VU.elt<uint16_t>(vd + fn, i) = val; + } else if (p->VU.vsew == e32) { + p->VU.elt<uint32_t>(vd + fn, i) = val; } else { - STATE.VU.elt<uint64_t>(vd + fn, i) = val; + p->VU.elt<uint64_t>(vd + fn, i) = val; } } } //zero unfilled part -for (reg_t i = vl; i < STATE.VU.vlmax; ++i) { +for (reg_t i = vl; i < p->VU.vlmax; ++i) { for (reg_t fn = 0; fn < nf; ++fn) { - if (STATE.VU.vsew == e8) { - STATE.VU.elt<uint8_t>(vd + fn, i) = 0; - } else if (STATE.VU.vsew == e16) { - STATE.VU.elt<uint16_t>(vd + fn, i) = 0; - } else if (STATE.VU.vsew == e32) { - STATE.VU.elt<uint32_t>(vd + fn, i) = 0; + if (p->VU.vsew == e8) { + p->VU.elt<uint8_t>(vd + fn, i) = 0; + } else if (p->VU.vsew == e16) { + p->VU.elt<uint16_t>(vd + fn, i) = 0; + } else if (p->VU.vsew == e32) { + p->VU.elt<uint32_t>(vd + fn, i) = 0; } else { - STATE.VU.elt<uint64_t>(vd + fn, i) = 0; + p->VU.elt<uint64_t>(vd + fn, i) = 0; } } } -STATE.VU.vstart = 0; +p->VU.vstart = 0; diff --git a/riscv/insns/vlxh_v.h b/riscv/insns/vlxh_v.h index 0406b39..7cf2be5 100644 --- a/riscv/insns/vlxh_v.h +++ b/riscv/insns/vlxh_v.h @@ -1,37 +1,37 @@ // vlxh.v and vlxseg[2-8]h.v -require(STATE.VU.vsew >= e16); +require(p->VU.vsew >= e16); reg_t nf = insn.v_nf() + 1; -require((nf >= 2 && STATE.VU.vlmul == 1) || nf == 1); -reg_t vl = STATE.VU.vl; +require((nf >= 2 && p->VU.vlmul == 1) || nf == 1); +reg_t vl = p->VU.vl; reg_t baseAddr = RS1; reg_t stride = insn.rs2(); reg_t vd = insn.rd(); -for (reg_t i = STATE.VU.vstart; i < vl; ++i) { +for (reg_t i = p->VU.vstart; i < vl; ++i) { V_LOOP_ELEMENT_SKIP; - reg_t index = STATE.VU.elt<int16_t>(stride, i); + reg_t index = p->VU.elt<int16_t>(stride, i); for (reg_t fn = 0; fn < nf; ++fn) { int64_t val = MMU.load_int16(baseAddr + index + fn * 2); - if (STATE.VU.vsew == e16) { - STATE.VU.elt<uint16_t>(vd + fn, i) = val; - } else if (STATE.VU.vsew == e32) { - STATE.VU.elt<uint32_t>(vd + fn, i) = val; + if (p->VU.vsew == e16) { + p->VU.elt<uint16_t>(vd + fn, i) = val; + } else if (p->VU.vsew == e32) { + p->VU.elt<uint32_t>(vd + fn, i) = val; } else { - STATE.VU.elt<uint64_t>(vd + fn, i) = val; + p->VU.elt<uint64_t>(vd + fn, i) = val; } } } //zero unfilled part -for (reg_t i = vl; i < STATE.VU.vlmax; ++i) { +for (reg_t i = vl; i < p->VU.vlmax; ++i) { for (reg_t fn = 0; fn < nf; ++fn) { - if (STATE.VU.vsew == e16) { - STATE.VU.elt<uint16_t>(vd + fn, i) = 0; - } else if (STATE.VU.vsew == e32) { - STATE.VU.elt<uint32_t>(vd + fn, i) = 0; + if (p->VU.vsew == e16) { + p->VU.elt<uint16_t>(vd + fn, i) = 0; + } else if (p->VU.vsew == e32) { + p->VU.elt<uint32_t>(vd + fn, i) = 0; } else { - STATE.VU.elt<uint64_t>(vd + fn, i) = 0; + p->VU.elt<uint64_t>(vd + fn, i) = 0; } } } -STATE.VU.vstart = 0; +p->VU.vstart = 0; diff --git a/riscv/insns/vlxhu_v.h b/riscv/insns/vlxhu_v.h index 83b3bf9..68c3077 100644 --- a/riscv/insns/vlxhu_v.h +++ b/riscv/insns/vlxhu_v.h @@ -1,37 +1,37 @@ // vlxh.v and vlxseg[2-8]h.v -require(STATE.VU.vsew >= e16); +require(p->VU.vsew >= e16); reg_t nf = insn.v_nf() + 1; -require((nf >= 2 && STATE.VU.vlmul == 1) || nf == 1); -reg_t vl = STATE.VU.vl; +require((nf >= 2 && p->VU.vlmul == 1) || nf == 1); +reg_t vl = p->VU.vl; reg_t baseAddr = RS1; reg_t stride = insn.rs2(); reg_t vd = insn.rd(); -for (reg_t i = STATE.VU.vstart; i < vl; ++i) { +for (reg_t i = p->VU.vstart; i < vl; ++i) { V_LOOP_ELEMENT_SKIP; - reg_t index = STATE.VU.elt<int16_t>(stride, i); + reg_t index = p->VU.elt<int16_t>(stride, i); for (reg_t fn = 0; fn < nf; ++fn) { uint64_t val = MMU.load_uint16(baseAddr + index + fn * 2); - if (STATE.VU.vsew == e16) { - STATE.VU.elt<uint16_t>(vd + fn, i) = val; - } else if (STATE.VU.vsew == e32) { - STATE.VU.elt<uint32_t>(vd + fn, i) = val; + if (p->VU.vsew == e16) { + p->VU.elt<uint16_t>(vd + fn, i) = val; + } else if (p->VU.vsew == e32) { + p->VU.elt<uint32_t>(vd + fn, i) = val; } else { - STATE.VU.elt<uint64_t>(vd + fn, i) = val; + p->VU.elt<uint64_t>(vd + fn, i) = val; } } } //zero unfilled part -for (reg_t i = vl; i < STATE.VU.vlmax; ++i) { +for (reg_t i = vl; i < p->VU.vlmax; ++i) { for (reg_t fn = 0; fn < nf; ++fn) { - if (STATE.VU.vsew == e16) { - STATE.VU.elt<uint16_t>(vd + fn, i) = 0; - } else if (STATE.VU.vsew == e32) { - STATE.VU.elt<uint32_t>(vd + fn, i) = 0; + if (p->VU.vsew == e16) { + p->VU.elt<uint16_t>(vd + fn, i) = 0; + } else if (p->VU.vsew == e32) { + p->VU.elt<uint32_t>(vd + fn, i) = 0; } else { - STATE.VU.elt<uint64_t>(vd + fn, i) = 0; + p->VU.elt<uint64_t>(vd + fn, i) = 0; } } } -STATE.VU.vstart = 0; +p->VU.vstart = 0; diff --git a/riscv/insns/vlxw_v.h b/riscv/insns/vlxw_v.h index fcead51..d521d83 100644 --- a/riscv/insns/vlxw_v.h +++ b/riscv/insns/vlxw_v.h @@ -1,33 +1,33 @@ // vlxw.v and vlxseg[2-8]w.v -require(STATE.VU.vsew >= e32); +require(p->VU.vsew >= e32); reg_t nf = insn.v_nf() + 1; -require((nf >= 2 && STATE.VU.vlmul == 1) || nf == 1); -reg_t vl = STATE.VU.vl; +require((nf >= 2 && p->VU.vlmul == 1) || nf == 1); +reg_t vl = p->VU.vl; reg_t baseAddr = RS1; reg_t stride = insn.rs2(); reg_t vd = insn.rd(); -for (reg_t i = STATE.VU.vstart; i < vl; ++i) { +for (reg_t i = p->VU.vstart; i < vl; ++i) { V_LOOP_ELEMENT_SKIP; - reg_t index = STATE.VU.elt<int32_t>(stride, i); + reg_t index = p->VU.elt<int32_t>(stride, i); for (reg_t fn = 0; fn < nf; ++fn) { int64_t val = MMU.load_int32(baseAddr + index + fn * 4); - if (STATE.VU.vsew == e32) { - STATE.VU.elt<uint32_t>(vd + fn, i) = val; + if (p->VU.vsew == e32) { + p->VU.elt<uint32_t>(vd + fn, i) = val; } else { - STATE.VU.elt<uint64_t>(vd + fn, i) = val; + p->VU.elt<uint64_t>(vd + fn, i) = val; } } } //zero unfilled part -for (reg_t i = vl; i < STATE.VU.vlmax; ++i) { +for (reg_t i = vl; i < p->VU.vlmax; ++i) { for (reg_t fn = 0; fn < nf; ++fn) { - if (STATE.VU.vsew == e32) { - STATE.VU.elt<uint32_t>(vd + fn, i) = 0; + if (p->VU.vsew == e32) { + p->VU.elt<uint32_t>(vd + fn, i) = 0; } else { - STATE.VU.elt<uint64_t>(vd + fn, i) = 0; + p->VU.elt<uint64_t>(vd + fn, i) = 0; } } } -STATE.VU.vstart = 0; +p->VU.vstart = 0; diff --git a/riscv/insns/vlxwu_v.h b/riscv/insns/vlxwu_v.h index 81a6203..53c138c 100644 --- a/riscv/insns/vlxwu_v.h +++ b/riscv/insns/vlxwu_v.h @@ -1,33 +1,33 @@ // vlxwu.v and vlxseg[2-8]wu.v -require(STATE.VU.vsew >= e32); +require(p->VU.vsew >= e32); reg_t nf = insn.v_nf() + 1; -require((nf >= 2 && STATE.VU.vlmul == 1) || nf == 1); -reg_t vl = STATE.VU.vl; +require((nf >= 2 && p->VU.vlmul == 1) || nf == 1); +reg_t vl = p->VU.vl; reg_t baseAddr = RS1; reg_t stride = insn.rs2(); reg_t vd = insn.rd(); -for (reg_t i = STATE.VU.vstart; i < vl; ++i) { +for (reg_t i = p->VU.vstart; i < vl; ++i) { V_LOOP_ELEMENT_SKIP; - reg_t index = STATE.VU.elt<int32_t>(stride, i); + reg_t index = p->VU.elt<int32_t>(stride, i); for (reg_t fn = 0; fn < nf; ++fn) { int64_t val = MMU.load_uint32(baseAddr + index + fn * 4); - if (STATE.VU.vsew == e32) { - STATE.VU.elt<uint32_t>(vd + fn, i) = val; + if (p->VU.vsew == e32) { + p->VU.elt<uint32_t>(vd + fn, i) = val; } else { - STATE.VU.elt<uint64_t>(vd + fn, i) = val; + p->VU.elt<uint64_t>(vd + fn, i) = val; } } } //zero unfilled part -for (reg_t i = vl; i < STATE.VU.vlmax; ++i) { +for (reg_t i = vl; i < p->VU.vlmax; ++i) { for (reg_t fn = 0; fn < nf; ++fn) { - if (STATE.VU.vsew == e32) { - STATE.VU.elt<uint32_t>(vd + fn, i) = 0; + if (p->VU.vsew == e32) { + p->VU.elt<uint32_t>(vd + fn, i) = 0; } else { - STATE.VU.elt<uint64_t>(vd + fn, i) = 0; + p->VU.elt<uint64_t>(vd + fn, i) = 0; } } } -STATE.VU.vstart = 0; +p->VU.vstart = 0; diff --git a/riscv/insns/vmerge_vi.h b/riscv/insns/vmerge_vi.h index db76af4..67dccb7 100644 --- a/riscv/insns/vmerge_vi.h +++ b/riscv/insns/vmerge_vi.h @@ -5,17 +5,17 @@ VI_VI_LOOP V_CHECK_MASK(do_mask); bool use_first = (insn.v_vm() == 1) || do_mask; - switch (STATE.VU.vsew) { + switch (p->VU.vsew) { case e8: - STATE.VU.elt<uint8_t>(rd_num, i) = use_first ? simm5 : vs2; + p->VU.elt<uint8_t>(rd_num, i) = use_first ? simm5 : vs2; break; case e16: - STATE.VU.elt<uint16_t>(rd_num, i) = use_first ? simm5 : vs2; + p->VU.elt<uint16_t>(rd_num, i) = use_first ? simm5 : vs2; break; case e32: - STATE.VU.elt<uint32_t>(rd_num, i) = use_first ? simm5 : vs2; + p->VU.elt<uint32_t>(rd_num, i) = use_first ? simm5 : vs2; break; default: - STATE.VU.elt<uint64_t>(rd_num, i) = use_first ? simm5 : vs2; + p->VU.elt<uint64_t>(rd_num, i) = use_first ? simm5 : vs2; } }) diff --git a/riscv/insns/vmerge_vv.h b/riscv/insns/vmerge_vv.h index 69ebae1..d4749b2 100644 --- a/riscv/insns/vmerge_vv.h +++ b/riscv/insns/vmerge_vv.h @@ -4,23 +4,23 @@ VI_VV_LOOP bool do_mask = false; if (insn.v_vm() == 0) { - int midx = (STATE.VU.vmlen * i) / 32; - int mpos = (STATE.VU.vmlen * i) % 32; - do_mask = (STATE.VU.elt<uint32_t>(0, midx) >> mpos) & 0x1; + int midx = (p->VU.vmlen * i) / 32; + int mpos = (p->VU.vmlen * i) % 32; + do_mask = (p->VU.elt<uint32_t>(0, midx) >> mpos) & 0x1; } bool use_first = (insn.v_vm() == 1) || do_mask; - switch (STATE.VU.vsew) { + switch (p->VU.vsew) { case e8: - STATE.VU.elt<uint8_t>(rd_num, i) = use_first ? vs1 : vs2; + p->VU.elt<uint8_t>(rd_num, i) = use_first ? vs1 : vs2; break; case e16: - STATE.VU.elt<uint16_t>(rd_num, i) = use_first ? vs1 : vs2; + p->VU.elt<uint16_t>(rd_num, i) = use_first ? vs1 : vs2; break; case e32: - STATE.VU.elt<uint32_t>(rd_num, i) = use_first ? vs1 : vs2; + p->VU.elt<uint32_t>(rd_num, i) = use_first ? vs1 : vs2; break; default: - STATE.VU.elt<uint64_t>(rd_num, i) = use_first ? vs1 : vs2; + p->VU.elt<uint64_t>(rd_num, i) = use_first ? vs1 : vs2; } }) diff --git a/riscv/insns/vmerge_vx.h b/riscv/insns/vmerge_vx.h index fd363bb..a16e8a5 100644 --- a/riscv/insns/vmerge_vx.h +++ b/riscv/insns/vmerge_vx.h @@ -5,17 +5,17 @@ VI_VX_LOOP V_CHECK_MASK(do_mask); bool use_first = (insn.v_vm() == 1) || do_mask; - switch (STATE.VU.vsew) { + switch (p->VU.vsew) { case e8: - STATE.VU.elt<uint8_t>(rd_num, i) = use_first ? rs1 : vs2; + p->VU.elt<uint8_t>(rd_num, i) = use_first ? rs1 : vs2; break; case e16: - STATE.VU.elt<uint16_t>(rd_num, i) = use_first ? rs1 : vs2; + p->VU.elt<uint16_t>(rd_num, i) = use_first ? rs1 : vs2; break; case e32: - STATE.VU.elt<uint32_t>(rd_num, i) = use_first ? rs1 : vs2; + p->VU.elt<uint32_t>(rd_num, i) = use_first ? rs1 : vs2; break; default: - STATE.VU.elt<uint64_t>(rd_num, i) = use_first ? rs1 : vs2; + p->VU.elt<uint64_t>(rd_num, i) = use_first ? rs1 : vs2; } }) diff --git a/riscv/insns/vmfirst_m.h b/riscv/insns/vmfirst_m.h index 7c9cf6e..07b5562 100644 --- a/riscv/insns/vmfirst_m.h +++ b/riscv/insns/vmfirst_m.h @@ -1,24 +1,24 @@ // vmfirst rd, vs2, vm -require(STATE.VU.vsew >= e8 && STATE.VU.vsew <= e64); -require(!STATE.VU.vill); -reg_t vl = STATE.VU.vl; -reg_t sew = STATE.VU.vsew; +require(p->VU.vsew >= e8 && p->VU.vsew <= e64); +require(!p->VU.vill); +reg_t vl = p->VU.vl; +reg_t sew = p->VU.vsew; reg_t rd_num = insn.rd(); reg_t rs2_num = insn.rs2(); -require(STATE.VU.vstart == 0); +require(p->VU.vstart == 0); reg_t pos = -1; -for (reg_t i=STATE.VU.vstart; i<vl; ++i){ - const int mlen = STATE.VU.vmlen; +for (reg_t i=p->VU.vstart; i<vl; ++i){ + const int mlen = p->VU.vmlen; const int midx = (mlen * i) / 32; const int mpos = (mlen * i) % 32; - bool vs2_lsb = ((STATE.VU.elt<uint32_t>(rs2_num, midx ) >> mpos) & 0x1) == 1; + bool vs2_lsb = ((p->VU.elt<uint32_t>(rs2_num, midx ) >> mpos) & 0x1) == 1; if (insn.v_vm() == 1) { pos = i; } else { - bool do_mask = (STATE.VU.elt<uint32_t>(0, midx) >> mpos) & 0x1; + bool do_mask = (p->VU.elt<uint32_t>(0, midx) >> mpos) & 0x1; pos = i; } } -STATE.VU.vstart = 0; +p->VU.vstart = 0; WRITE_RD(pos); diff --git a/riscv/insns/vmpopc_m.h b/riscv/insns/vmpopc_m.h index 7a9774e..acd666e 100644 --- a/riscv/insns/vmpopc_m.h +++ b/riscv/insns/vmpopc_m.h @@ -1,24 +1,24 @@ // vmpopc rd, vs2, vm -require(STATE.VU.vsew >= e8 && STATE.VU.vsew <= e64); -require(!STATE.VU.vill); -reg_t vl = STATE.VU.vl; -reg_t sew = STATE.VU.vsew; +require(p->VU.vsew >= e8 && p->VU.vsew <= e64); +require(!p->VU.vill); +reg_t vl = p->VU.vl; +reg_t sew = p->VU.vsew; reg_t rd_num = insn.rd(); reg_t rs2_num = insn.rs2(); -require(STATE.VU.vstart == 0); +require(p->VU.vstart == 0); reg_t popcount = 0; -for (reg_t i=STATE.VU.vstart; i<vl; ++i){ - const int mlen = STATE.VU.vmlen; +for (reg_t i=p->VU.vstart; i<vl; ++i){ + const int mlen = p->VU.vmlen; const int midx = (mlen * i) / 32; const int mpos = (mlen * i) % 32; - bool vs2_lsb = ((STATE.VU.elt<uint32_t>(rs2_num, midx ) >> mpos) & 0x1) == 1; + bool vs2_lsb = ((p->VU.elt<uint32_t>(rs2_num, midx ) >> mpos) & 0x1) == 1; if (insn.v_vm() == 1) { popcount += vs2_lsb; } else { - bool do_mask = (STATE.VU.elt<uint32_t>(0, midx) >> mpos) & 0x1; + bool do_mask = (p->VU.elt<uint32_t>(0, midx) >> mpos) & 0x1; popcount += (vs2_lsb && do_mask); } } -STATE.VU.vstart = 0; +p->VU.vstart = 0; WRITE_RD(popcount); diff --git a/riscv/insns/vmul_vv.h b/riscv/insns/vmul_vv.h index 2d4bc4e..2cee1c9 100644 --- a/riscv/insns/vmul_vv.h +++ b/riscv/insns/vmul_vv.h @@ -1,5 +1,5 @@ // vmul -reg_t vsew = STATE.VU.vsew; +reg_t vsew = p->VU.vsew; uint64_t lo_mask = ((uint64_t)1 << vsew) - 1; VI_VV_LOOP diff --git a/riscv/insns/vmul_vx.h b/riscv/insns/vmul_vx.h index 0a77af0..931ddc4 100644 --- a/riscv/insns/vmul_vx.h +++ b/riscv/insns/vmul_vx.h @@ -1,5 +1,5 @@ // vmul -reg_t vsew = STATE.VU.vsew; +reg_t vsew = p->VU.vsew; uint64_t lo_mask = ((uint64_t)1 << vsew) - 1; VI_VX_LOOP diff --git a/riscv/insns/vmulh_vv.h b/riscv/insns/vmulh_vv.h index 4f3c01c..a5a793b 100644 --- a/riscv/insns/vmulh_vv.h +++ b/riscv/insns/vmulh_vv.h @@ -1,5 +1,5 @@ // vmulh -reg_t vsew = STATE.VU.vsew; +reg_t vsew = p->VU.vsew; uint64_t lo_mask = ((uint64_t)1 << vsew) - 1; VI_VV_LOOP diff --git a/riscv/insns/vmulh_vx.h b/riscv/insns/vmulh_vx.h index 1898950..ea06b21 100644 --- a/riscv/insns/vmulh_vx.h +++ b/riscv/insns/vmulh_vx.h @@ -1,5 +1,5 @@ // vmulh -reg_t vsew = STATE.VU.vsew; +reg_t vsew = p->VU.vsew; uint64_t lo_mask = ((uint64_t)1 << vsew) - 1; VI_VX_LOOP diff --git a/riscv/insns/vmulhsu_vv.h b/riscv/insns/vmulhsu_vv.h index d87a85d..cc46647 100644 --- a/riscv/insns/vmulhsu_vv.h +++ b/riscv/insns/vmulhsu_vv.h @@ -1,6 +1,6 @@ // vmulhsu: Signed multiply, returning high bits of product -require(STATE.VU.ELEN <= 32); -reg_t vsew = STATE.VU.vsew; +require(p->VU.ELEN <= 32); +reg_t vsew = p->VU.vsew; uint64_t umax = -1; uint64_t lo_mask = (((uint64_t)1 << vsew) - 1); uint64_t double_mask = (vsew == 32)? umax: ((uint64_t)1 << 2*vsew) - 1; diff --git a/riscv/insns/vmulhsu_vx.h b/riscv/insns/vmulhsu_vx.h index 6b18e0e..2592936 100644 --- a/riscv/insns/vmulhsu_vx.h +++ b/riscv/insns/vmulhsu_vx.h @@ -1,6 +1,6 @@ // vmulhsu: Signed multiply, returning high bits of product -require(STATE.VU.ELEN <= 32); -reg_t vsew = STATE.VU.vsew; +require(p->VU.ELEN <= 32); +reg_t vsew = p->VU.vsew; uint64_t umax = -1; uint64_t lo_mask = (((uint64_t)1 << vsew) - 1); uint64_t double_mask = (vsew == 32)? umax: ((uint64_t)1 << 2*vsew) - 1; diff --git a/riscv/insns/vmulhu_vv.h b/riscv/insns/vmulhu_vv.h index 885fddf..b4669ea 100644 --- a/riscv/insns/vmulhu_vv.h +++ b/riscv/insns/vmulhu_vv.h @@ -1,6 +1,6 @@ // vmulhu: Unsigned multiply, returning high bits of product -require(STATE.VU.ELEN <= 32); -reg_t vsew = STATE.VU.vsew; +require(p->VU.ELEN <= 32); +reg_t vsew = p->VU.vsew; uint64_t lo_mask = (((uint64_t)1 << vsew) - 1); VI_VV_ULOOP diff --git a/riscv/insns/vmulhu_vx.h b/riscv/insns/vmulhu_vx.h index c31bd89..3d415d1 100644 --- a/riscv/insns/vmulhu_vx.h +++ b/riscv/insns/vmulhu_vx.h @@ -1,6 +1,6 @@ // vmulhu: Unsigned multiply, returning high bits of product -require(STATE.VU.ELEN <= 32); -reg_t vsew = STATE.VU.vsew; +require(p->VU.ELEN <= 32); +reg_t vsew = p->VU.vsew; uint64_t lo_mask = (((uint64_t)1 << vsew) - 1); VI_VX_ULOOP diff --git a/riscv/insns/vmv_s_x.h b/riscv/insns/vmv_s_x.h index d3492d6..c384041 100644 --- a/riscv/insns/vmv_s_x.h +++ b/riscv/insns/vmv_s_x.h @@ -1,41 +1,41 @@ // vmv_s_x: vd[0] = rs1 -require(STATE.VU.vsew == e8 || STATE.VU.vsew == e16 || - STATE.VU.vsew == e32 || STATE.VU.vsew == e64); -reg_t vl = STATE.VU.vl; +require(p->VU.vsew == e8 || p->VU.vsew == e16 || + p->VU.vsew == e32 || p->VU.vsew == e64); +reg_t vl = p->VU.vl; if (vl > 0) { reg_t rd_num = insn.rd(); - reg_t sew = STATE.VU.vsew; + reg_t sew = p->VU.vsew; switch(sew) { case e8: - STATE.VU.elt<uint8_t>(rd_num, 0) = RS1; + p->VU.elt<uint8_t>(rd_num, 0) = RS1; break; case e16: - STATE.VU.elt<uint16_t>(rd_num, 0) = RS1; + p->VU.elt<uint16_t>(rd_num, 0) = RS1; break; case e32: - STATE.VU.elt<uint32_t>(rd_num, 0) = RS1; + p->VU.elt<uint32_t>(rd_num, 0) = RS1; break; default: - STATE.VU.elt<uint64_t>(rd_num, 0) = RS1; + p->VU.elt<uint64_t>(rd_num, 0) = RS1; break; } - const reg_t max_len = STATE.VU.VLEN / sew; + const reg_t max_len = p->VU.VLEN / sew; for (reg_t i = 1; i < max_len; ++i){ switch(sew) { case e8: - STATE.VU.elt<uint8_t>(rd_num, i) = 0; + p->VU.elt<uint8_t>(rd_num, i) = 0; break; case e16: - STATE.VU.elt<uint16_t>(rd_num, i) = 0; + p->VU.elt<uint16_t>(rd_num, i) = 0; break; case e32: - STATE.VU.elt<uint32_t>(rd_num, i) = 0; + p->VU.elt<uint32_t>(rd_num, i) = 0; break; default: - STATE.VU.elt<uint64_t>(rd_num, i) = 0; + p->VU.elt<uint64_t>(rd_num, i) = 0; break; } } diff --git a/riscv/insns/vnclip_vi.h b/riscv/insns/vnclip_vi.h index e9f7508..70ba915 100644 --- a/riscv/insns/vnclip_vi.h +++ b/riscv/insns/vnclip_vi.h @@ -1,7 +1,7 @@ // vnclip: vd[i] = clip(round(vs2[i] + rnd) >> simm) -VRM xrm = STATE.VU.get_vround_mode(); -uint64_t int_max = (1 << (STATE.VU.vsew - 1)) - 1; -uint64_t unsigned_mask = ~(-1 << (STATE.VU.vsew - 1)); +VRM xrm = p->VU.get_vround_mode(); +uint64_t int_max = (1 << (p->VU.vsew - 1)) - 1; +uint64_t unsigned_mask = ~(-1 << (p->VU.vsew - 1)); VI_VI_LOOP ({ uint64_t result = (vs2 & unsigned_mask) << sew; // expend the vs2 size more than SEW @@ -14,7 +14,7 @@ VI_VI_LOOP // saturation if ((result & ((int64_t)-1 << sew)) != 0){ result = sign | int_max; - STATE.VU.vxsat = 1; + p->VU.vxsat = 1; } else if (sign > 0){ result = vsext(result|sign, sew); } diff --git a/riscv/insns/vnclip_vv.h b/riscv/insns/vnclip_vv.h index 2b50a40..6d8bd98 100644 --- a/riscv/insns/vnclip_vv.h +++ b/riscv/insns/vnclip_vv.h @@ -1,7 +1,7 @@ // vnclip: vd[i] = clip(round(vs2[i] + rnd) >> vs1[i]) -VRM xrm = STATE.VU.get_vround_mode(); -uint64_t int_max = (1 << (STATE.VU.vsew - 1)) - 1; -uint64_t unsigned_mask = ~(-1 << (STATE.VU.vsew - 1)); +VRM xrm = p->VU.get_vround_mode(); +uint64_t int_max = (1 << (p->VU.vsew - 1)) - 1; +uint64_t unsigned_mask = ~(-1 << (p->VU.vsew - 1)); VI_VV_LOOP ({ uint64_t result = (vs2 & unsigned_mask) << sew; // expend the vs2 size more than SEW @@ -14,7 +14,7 @@ VI_VV_LOOP // saturation if ((result & ((int64_t)-1 << sew)) != 0){ result = sign | int_max; - STATE.VU.vxsat = 1; + p->VU.vxsat = 1; } else if (sign > 0){ result = vsext(result|sign, sew); } diff --git a/riscv/insns/vnclip_vx.h b/riscv/insns/vnclip_vx.h index 13b156c..00d7b2e 100644 --- a/riscv/insns/vnclip_vx.h +++ b/riscv/insns/vnclip_vx.h @@ -1,7 +1,7 @@ // vnclip: vd[i] = clip(round(vs2[i] + rnd) >> rs1[i]) -VRM xrm = STATE.VU.get_vround_mode(); -uint64_t int_max = (1 << (STATE.VU.vsew - 1)) - 1; -uint64_t unsigned_mask = ~(-1 << (STATE.VU.vsew - 1)); +VRM xrm = p->VU.get_vround_mode(); +uint64_t int_max = (1 << (p->VU.vsew - 1)) - 1; +uint64_t unsigned_mask = ~(-1 << (p->VU.vsew - 1)); VI_VX_LOOP ({ uint64_t result = (vs2 & unsigned_mask) << sew; // expend the vs2 size more than SEW @@ -14,7 +14,7 @@ VI_VX_LOOP // saturation if ((result & ((int64_t)-1 << sew)) != 0){ result = sign | int_max; - STATE.VU.vxsat = 1; + p->VU.vxsat = 1; } else if (sign > 0){ result = vsext(result|sign, sew); } diff --git a/riscv/insns/vnclipu_vi.h b/riscv/insns/vnclipu_vi.h index c3af93e..d805291 100644 --- a/riscv/insns/vnclipu_vi.h +++ b/riscv/insns/vnclipu_vi.h @@ -1,6 +1,6 @@ // vnclipu: vd[i] = clip(round(vs2[i] + rnd) >> simm) -VRM xrm = STATE.VU.get_vround_mode(); -uint64_t int_max = ~(-1ll << STATE.VU.vsew); +VRM xrm = p->VU.get_vround_mode(); +uint64_t int_max = ~(-1ll << p->VU.vsew); VI_VI_ULOOP ({ uint64_t result = (vs2 + 0llu) << sew; // expend the vs2 size more than SEW @@ -13,7 +13,7 @@ VI_VI_ULOOP // saturation if (result & (uint64_t)(-1ll << sew)){ result = int_max; - STATE.VU.vxsat = 1; + p->VU.vxsat = 1; } vd = result; diff --git a/riscv/insns/vnclipu_vv.h b/riscv/insns/vnclipu_vv.h index 7570f20..042f59f 100644 --- a/riscv/insns/vnclipu_vv.h +++ b/riscv/insns/vnclipu_vv.h @@ -1,6 +1,6 @@ // vnclipu: vd[i] = clip(round(vs2[i] + rnd) >> vs1[i]) -VRM xrm = STATE.VU.get_vround_mode(); -uint64_t int_max = ~(-1ll << STATE.VU.vsew); +VRM xrm = p->VU.get_vround_mode(); +uint64_t int_max = ~(-1ll << p->VU.vsew); VI_VV_ULOOP ({ uint64_t result = (vs2 + 0llu) << sew; // expend the vs2 size more than SEW @@ -13,7 +13,7 @@ VI_VV_ULOOP // saturation if (result & (uint64_t)(-1ll << sew)){ result = int_max; - STATE.VU.vxsat = 1; + p->VU.vxsat = 1; } vd = result; diff --git a/riscv/insns/vnclipu_vx.h b/riscv/insns/vnclipu_vx.h index 7e95192..5512e42 100644 --- a/riscv/insns/vnclipu_vx.h +++ b/riscv/insns/vnclipu_vx.h @@ -1,6 +1,6 @@ // vnclipu: vd[i] = clip(round(vs2[i] + rnd) >> rs1[i]) -VRM xrm = STATE.VU.get_vround_mode(); -uint64_t int_max = ~(-1ll << STATE.VU.vsew); +VRM xrm = p->VU.get_vround_mode(); +uint64_t int_max = ~(-1ll << p->VU.vsew); VI_VX_ULOOP ({ uint64_t result = (vs2 + 0llu) << sew; // expend the vs2 size more than SEW @@ -13,7 +13,7 @@ VI_VX_ULOOP // saturation if (result & (uint64_t)(-1ll << sew)){ result = int_max; - STATE.VU.vxsat = 1; + p->VU.vxsat = 1; } vd = result; diff --git a/riscv/insns/vsaddu_vi.h b/riscv/insns/vsaddu_vi.h index 874229f..ade91fe 100644 --- a/riscv/insns/vsaddu_vi.h +++ b/riscv/insns/vsaddu_vi.h @@ -7,5 +7,5 @@ VI_VI_ULOOP sat = vd < vs2; vd |= -(vd < vs2); - STATE.VU.vxsat |= sat; + p->VU.vxsat |= sat; }) diff --git a/riscv/insns/vsaddu_vv.h b/riscv/insns/vsaddu_vv.h index 9e935c7..9a2333e 100644 --- a/riscv/insns/vsaddu_vv.h +++ b/riscv/insns/vsaddu_vv.h @@ -7,5 +7,5 @@ VI_VV_ULOOP sat = vd < vs2; vd |= -(vd < vs2); - STATE.VU.vxsat |= sat; + p->VU.vxsat |= sat; }) diff --git a/riscv/insns/vsaddu_vx.h b/riscv/insns/vsaddu_vx.h index 450e6a2..277e082 100644 --- a/riscv/insns/vsaddu_vx.h +++ b/riscv/insns/vsaddu_vx.h @@ -7,6 +7,6 @@ VI_VX_ULOOP sat = vd < vs2; vd |= -(vd < vs2); - STATE.VU.vxsat |= sat; + p->VU.vxsat |= sat; }) diff --git a/riscv/insns/vsb_v.h b/riscv/insns/vsb_v.h index 8e0d526..fbae241 100644 --- a/riscv/insns/vsb_v.h +++ b/riscv/insns/vsb_v.h @@ -1,30 +1,30 @@ // vsb.v and vsseg[2-8]b.v -require(STATE.VU.vsew >= e8); +require(p->VU.vsew >= e8); reg_t nf = insn.v_nf() + 1; -require((nf >= 2 && STATE.VU.vlmul == 1) || nf == 1); -reg_t vl = STATE.VU.vl; +require((nf >= 2 && p->VU.vlmul == 1) || nf == 1); +reg_t vl = p->VU.vl; reg_t baseAddr = RS1; reg_t vs3 = insn.rd(); -for (reg_t i = STATE.VU.vstart; i < vl; ++i) { +for (reg_t i = p->VU.vstart; i < vl; ++i) { V_LOOP_ELEMENT_SKIP; for (reg_t fn = 0; fn < nf; ++fn) { uint8_t val = 0; - switch (STATE.VU.vsew) { + switch (p->VU.vsew) { case e8: - val = STATE.VU.elt<uint8_t>(vs3 + fn, i); + val = p->VU.elt<uint8_t>(vs3 + fn, i); break; case e16: - val = STATE.VU.elt<uint16_t>(vs3 + fn, i); + val = p->VU.elt<uint16_t>(vs3 + fn, i); break; case e32: - val = STATE.VU.elt<uint32_t>(vs3 + fn, i); + val = p->VU.elt<uint32_t>(vs3 + fn, i); break; defaualt: - val = STATE.VU.elt<uint64_t>(vs3 + fn, i); + val = p->VU.elt<uint64_t>(vs3 + fn, i); break; } MMU.store_uint8(baseAddr + (i * nf + fn) * 1, val); } } -STATE.VU.vstart = 0; +p->VU.vstart = 0; diff --git a/riscv/insns/vsetvl.h b/riscv/insns/vsetvl.h index b4da843..429e5c0 100644 --- a/riscv/insns/vsetvl.h +++ b/riscv/insns/vsetvl.h @@ -1 +1 @@ -WRITE_RD(STATE.VU.set_vl(insn.rs1(), RS1, RS2)); +WRITE_RD(p->VU.set_vl(insn.rs1(), RS1, RS2)); diff --git a/riscv/insns/vsetvli.h b/riscv/insns/vsetvli.h index 9bc32cd..0f4d4a6 100644 --- a/riscv/insns/vsetvli.h +++ b/riscv/insns/vsetvli.h @@ -1 +1 @@ -WRITE_RD(STATE.VU.set_vl(insn.rs1(), RS1, insn.v_zimm11())); +WRITE_RD(p->VU.set_vl(insn.rs1(), RS1, insn.v_zimm11())); diff --git a/riscv/insns/vsh_v.h b/riscv/insns/vsh_v.h index e7780b2..9aeb740 100644 --- a/riscv/insns/vsh_v.h +++ b/riscv/insns/vsh_v.h @@ -1,27 +1,27 @@ // vsh.v and vsseg[2-8]h.v -require(STATE.VU.vsew >= e16); +require(p->VU.vsew >= e16); reg_t nf = insn.v_nf() + 1; -require((nf >= 2 && STATE.VU.vlmul == 1) || nf == 1); -reg_t vl = STATE.VU.vl; +require((nf >= 2 && p->VU.vlmul == 1) || nf == 1); +reg_t vl = p->VU.vl; reg_t baseAddr = RS1; reg_t vs3 = insn.rd(); -for (reg_t i = STATE.VU.vstart; i < vl; ++i) { +for (reg_t i = p->VU.vstart; i < vl; ++i) { V_LOOP_ELEMENT_SKIP; for (reg_t fn = 0; fn < nf; ++fn) { uint16_t val = 0; - switch (STATE.VU.vsew) { + switch (p->VU.vsew) { case e16: - val = STATE.VU.elt<uint16_t>(vs3 + fn, i); + val = p->VU.elt<uint16_t>(vs3 + fn, i); break; case e32: - val = STATE.VU.elt<uint32_t>(vs3 + fn, i); + val = p->VU.elt<uint32_t>(vs3 + fn, i); break; defaualt: - val = STATE.VU.elt<uint64_t>(vs3 + fn, i); + val = p->VU.elt<uint64_t>(vs3 + fn, i); break; } MMU.store_uint16(baseAddr + (i * nf + fn) * 2, val); } } -STATE.VU.vstart = 0; +p->VU.vstart = 0; diff --git a/riscv/insns/vsmul_vv.h b/riscv/insns/vsmul_vv.h index 395a1b3..a30eced 100644 --- a/riscv/insns/vsmul_vv.h +++ b/riscv/insns/vsmul_vv.h @@ -1,9 +1,9 @@ // vsmul: Signed saturating and rounding fractional multiply -VRM xrm = STATE.VU.get_vround_mode(); -int64_t int_max = (1 << STATE.VU.vsew) - 1; -int64_t int_min = - (1 << (STATE.VU.vsew - 1)); -int64_t val_mask = ((1 << (STATE.VU.vsew - 1)) - 1); -int64_t sign_mask = ((1 << (STATE.VU.vsew - 1))); +VRM xrm = p->VU.get_vround_mode(); +int64_t int_max = (1 << p->VU.vsew) - 1; +int64_t int_min = - (1 << (p->VU.vsew - 1)); +int64_t val_mask = ((1 << (p->VU.vsew - 1)) - 1); +int64_t sign_mask = ((1 << (p->VU.vsew - 1))); VI_VV_LOOP ({ @@ -33,7 +33,7 @@ VI_VV_LOOP }else{ result = int_min; } - STATE.VU.vxsat = 1; + p->VU.vxsat = 1; } vd = result; }) diff --git a/riscv/insns/vsmul_vx.h b/riscv/insns/vsmul_vx.h index 7998868..12491b6 100644 --- a/riscv/insns/vsmul_vx.h +++ b/riscv/insns/vsmul_vx.h @@ -1,9 +1,9 @@ // vsmul -VRM xrm = STATE.VU.get_vround_mode(); -int64_t int_max = (1 << STATE.VU.vsew) - 1; -int64_t int_min = - (1 << (STATE.VU.vsew - 1)); -int64_t val_mask = ((1 << (STATE.VU.vsew - 1)) - 1); -int64_t sign_mask = ((1 << (STATE.VU.vsew - 1))); +VRM xrm = p->VU.get_vround_mode(); +int64_t int_max = (1 << p->VU.vsew) - 1; +int64_t int_min = - (1 << (p->VU.vsew - 1)); +int64_t val_mask = ((1 << (p->VU.vsew - 1)) - 1); +int64_t sign_mask = ((1 << (p->VU.vsew - 1))); VI_VX_LOOP ({ @@ -32,7 +32,7 @@ VI_VX_LOOP }else{ result = int_min; } - STATE.VU.vxsat = 1; + p->VU.vxsat = 1; } vd = result; }) diff --git a/riscv/insns/vssb_v.h b/riscv/insns/vssb_v.h index d7f22a8..1088a58 100644 --- a/riscv/insns/vssb_v.h +++ b/riscv/insns/vssb_v.h @@ -1,32 +1,32 @@ // vssb.v and vssseg[2-8]b.v -require(STATE.VU.vsew >= e8); +require(p->VU.vsew >= e8); reg_t nf = insn.v_nf() + 1; -require((nf >= 2 && STATE.VU.vlmul == 1) || nf == 1); -reg_t vl = STATE.VU.vl; +require((nf >= 2 && p->VU.vlmul == 1) || nf == 1); +reg_t vl = p->VU.vl; reg_t baseAddr = RS1; reg_t stride = RS2; reg_t vs3 = insn.rd(); -for (reg_t i = STATE.VU.vstart; i < vl; ++i) { +for (reg_t i = p->VU.vstart; i < vl; ++i) { V_LOOP_ELEMENT_SKIP; for (reg_t fn = 0; fn < nf; ++fn) { uint8_t val = 0; - switch (STATE.VU.vsew) { + switch (p->VU.vsew) { case e8: - val = STATE.VU.elt<uint8_t>(vs3 + fn, i); + val = p->VU.elt<uint8_t>(vs3 + fn, i); break; case e16: - val = STATE.VU.elt<uint16_t>(vs3 + fn, i); + val = p->VU.elt<uint16_t>(vs3 + fn, i); break; case e32: - val = STATE.VU.elt<uint32_t>(vs3 + fn, i); + val = p->VU.elt<uint32_t>(vs3 + fn, i); break; defaualt: - val = STATE.VU.elt<uint64_t>(vs3 + fn, i); + val = p->VU.elt<uint64_t>(vs3 + fn, i); break; } MMU.store_uint8(baseAddr + i * stride + fn * 1, val); } } -STATE.VU.vstart = 0; +p->VU.vstart = 0; diff --git a/riscv/insns/vssh_v.h b/riscv/insns/vssh_v.h index 345f287..3fc6956 100644 --- a/riscv/insns/vssh_v.h +++ b/riscv/insns/vssh_v.h @@ -1,28 +1,28 @@ // vssh.v and vssseg[2-8]h.v -require(STATE.VU.vsew >= e16); +require(p->VU.vsew >= e16); reg_t nf = insn.v_nf() + 1; -require((nf >= 2 && STATE.VU.vlmul == 1) || nf == 1); -reg_t vl = STATE.VU.vl; +require((nf >= 2 && p->VU.vlmul == 1) || nf == 1); +reg_t vl = p->VU.vl; reg_t baseAddr = RS1; reg_t stride = RS2; reg_t vs3 = insn.rd(); -for (reg_t i = STATE.VU.vstart; i < vl; ++i) { +for (reg_t i = p->VU.vstart; i < vl; ++i) { V_LOOP_ELEMENT_SKIP; for (reg_t fn = 0; fn < nf; ++fn) { uint16_t val = 0; - switch (STATE.VU.vsew) { + switch (p->VU.vsew) { case e16: - val = STATE.VU.elt<uint16_t>(vs3 + fn, i); + val = p->VU.elt<uint16_t>(vs3 + fn, i); break; case e32: - val = STATE.VU.elt<uint32_t>(vs3 + fn, i); + val = p->VU.elt<uint32_t>(vs3 + fn, i); break; defaualt: - val = STATE.VU.elt<uint64_t>(vs3 + fn, i); + val = p->VU.elt<uint64_t>(vs3 + fn, i); break; } MMU.store_uint16(baseAddr + i * stride + fn * 2, val); } } -STATE.VU.vstart = 0; +p->VU.vstart = 0; diff --git a/riscv/insns/vssub_vv.h b/riscv/insns/vssub_vv.h index cc0eeb2..6175acb 100644 --- a/riscv/insns/vssub_vv.h +++ b/riscv/insns/vssub_vv.h @@ -24,5 +24,5 @@ VI_LOOP_BASE break; } } - STATE.VU.vxsat |= sat; + p->VU.vxsat |= sat; VI_LOOP_END diff --git a/riscv/insns/vssub_vx.h b/riscv/insns/vssub_vx.h index 56c22fa..709008a 100644 --- a/riscv/insns/vssub_vx.h +++ b/riscv/insns/vssub_vx.h @@ -24,5 +24,5 @@ VI_LOOP_BASE break; } } - STATE.VU.vxsat |= sat; + p->VU.vxsat |= sat; VI_LOOP_END diff --git a/riscv/insns/vssubu_vv.h b/riscv/insns/vssubu_vv.h index fdb439e..a53f8e5 100644 --- a/riscv/insns/vssubu_vv.h +++ b/riscv/insns/vssubu_vv.h @@ -25,6 +25,6 @@ VI_LOOP_BASE break; } } - STATE.VU.vxsat |= sat; + p->VU.vxsat |= sat; VI_LOOP_END diff --git a/riscv/insns/vssubu_vx.h b/riscv/insns/vssubu_vx.h index 9f1870e..5304ec0 100644 --- a/riscv/insns/vssubu_vx.h +++ b/riscv/insns/vssubu_vx.h @@ -24,5 +24,5 @@ VI_LOOP_BASE break; } } - STATE.VU.vxsat |= sat; + p->VU.vxsat |= sat; VI_LOOP_END diff --git a/riscv/insns/vssw_v.h b/riscv/insns/vssw_v.h index 2f1190f..0ff5df5 100644 --- a/riscv/insns/vssw_v.h +++ b/riscv/insns/vssw_v.h @@ -1,25 +1,25 @@ // vssw.v and vssseg[2-8]w.v -require(STATE.VU.vsew >= e32); +require(p->VU.vsew >= e32); reg_t nf = insn.v_nf() + 1; -require((nf >= 2 && STATE.VU.vlmul == 1) || nf == 1); -reg_t vl = STATE.VU.vl; +require((nf >= 2 && p->VU.vlmul == 1) || nf == 1); +reg_t vl = p->VU.vl; reg_t baseAddr = RS1; reg_t stride = RS2; reg_t vs3 = insn.rd(); -for (reg_t i = STATE.VU.vstart; i < vl; ++i) { +for (reg_t i = p->VU.vstart; i < vl; ++i) { V_LOOP_ELEMENT_SKIP; for (reg_t fn = 0; fn < nf; ++fn) { uint32_t val = 0; - switch (STATE.VU.vsew) { + switch (p->VU.vsew) { case e32: - val = STATE.VU.elt<uint32_t>(vs3 + fn, i); + val = p->VU.elt<uint32_t>(vs3 + fn, i); break; defaualt: - val = STATE.VU.elt<uint64_t>(vs3 + fn, i); + val = p->VU.elt<uint64_t>(vs3 + fn, i); break; } MMU.store_uint32(baseAddr + i * stride + fn * 4, val); } } -STATE.VU.vstart = 0; +p->VU.vstart = 0; diff --git a/riscv/insns/vsw_v.h b/riscv/insns/vsw_v.h index 26ccbdb..a3a54fa 100644 --- a/riscv/insns/vsw_v.h +++ b/riscv/insns/vsw_v.h @@ -1,24 +1,24 @@ // vsw.v and vsseg[2-8]w.v -require(STATE.VU.vsew >= e32); +require(p->VU.vsew >= e32); reg_t nf = insn.v_nf() + 1; -require((nf >= 2 && STATE.VU.vlmul == 1) || nf == 1); -reg_t vl = STATE.VU.vl; +require((nf >= 2 && p->VU.vlmul == 1) || nf == 1); +reg_t vl = p->VU.vl; reg_t baseAddr = RS1; reg_t vs3 = insn.rd(); -for (reg_t i = STATE.VU.vstart; i < vl; ++i){ +for (reg_t i = p->VU.vstart; i < vl; ++i){ V_LOOP_ELEMENT_SKIP; for (reg_t fn = 0; fn < nf; ++fn){ uint32_t val = 0; - switch (STATE.VU.vsew) { + switch (p->VU.vsew) { case e32: - val = STATE.VU.elt<uint32_t>(vs3 + fn, i); + val = p->VU.elt<uint32_t>(vs3 + fn, i); break; defaualt: - val = STATE.VU.elt<uint64_t>(vs3 + fn, i); + val = p->VU.elt<uint64_t>(vs3 + fn, i); break; } MMU.store_uint32(baseAddr + (i * nf + fn) * 4, val); } } -STATE.VU.vstart = 0; +p->VU.vstart = 0; diff --git a/riscv/insns/vsxb_v.h b/riscv/insns/vsxb_v.h index 569847e..420d4d4 100644 --- a/riscv/insns/vsxb_v.h +++ b/riscv/insns/vsxb_v.h @@ -1,32 +1,32 @@ // vsxb.v and vsxseg[2-8]b.v -require(STATE.VU.vsew >= e8); +require(p->VU.vsew >= e8); reg_t nf = insn.v_nf() + 1; -require((nf >= 2 && STATE.VU.vlmul == 1) || nf == 1); -reg_t vl = STATE.VU.vl; +require((nf >= 2 && p->VU.vlmul == 1) || nf == 1); +reg_t vl = p->VU.vl; reg_t baseAddr = RS1; reg_t stride = insn.rs2(); reg_t vs3 = insn.rd(); -for (reg_t i = STATE.VU.vstart; i < vl; ++i) { +for (reg_t i = p->VU.vstart; i < vl; ++i) { V_LOOP_ELEMENT_SKIP; - reg_t index = STATE.VU.elt<int8_t>(stride, i); + reg_t index = p->VU.elt<int8_t>(stride, i); for (reg_t fn = 0; fn < nf; ++fn) { uint8_t val = 0; - switch (STATE.VU.vsew) { + switch (p->VU.vsew) { case e8: - val = STATE.VU.elt<uint8_t>(vs3 + fn, i); + val = p->VU.elt<uint8_t>(vs3 + fn, i); break; case e16: - val = STATE.VU.elt<uint16_t>(vs3 + fn, i); + val = p->VU.elt<uint16_t>(vs3 + fn, i); break; case e32: - val = STATE.VU.elt<uint32_t>(vs3 + fn, i); + val = p->VU.elt<uint32_t>(vs3 + fn, i); break; defaualt: - val = STATE.VU.elt<uint64_t>(vs3 + fn, i); + val = p->VU.elt<uint64_t>(vs3 + fn, i); break; } MMU.store_uint8(baseAddr + index + fn * 1, val); } } -STATE.VU.vstart = 0; +p->VU.vstart = 0; diff --git a/riscv/insns/vsxh_v.h b/riscv/insns/vsxh_v.h index 16609f0..8d1a8bb 100644 --- a/riscv/insns/vsxh_v.h +++ b/riscv/insns/vsxh_v.h @@ -1,29 +1,29 @@ // vsxh.v and vsxseg[2-8]h.v -require(STATE.VU.vsew >= e16); +require(p->VU.vsew >= e16); reg_t nf = insn.v_nf() + 1; -require((nf >= 2 && STATE.VU.vlmul == 1) || nf == 1); -reg_t vl = STATE.VU.vl; +require((nf >= 2 && p->VU.vlmul == 1) || nf == 1); +reg_t vl = p->VU.vl; reg_t baseAddr = RS1; reg_t stride = insn.rs2(); reg_t vs3 = insn.rd(); -for (reg_t i = STATE.VU.vstart; i < vl; ++i) { +for (reg_t i = p->VU.vstart; i < vl; ++i) { V_LOOP_ELEMENT_SKIP; - reg_t index = STATE.VU.elt<int16_t>(stride, i); + reg_t index = p->VU.elt<int16_t>(stride, i); for (reg_t fn = 0; fn < nf; ++fn) { uint16_t val = 0; - switch (STATE.VU.vsew) { + switch (p->VU.vsew) { case e16: - val = STATE.VU.elt<uint16_t>(vs3 + fn, i); + val = p->VU.elt<uint16_t>(vs3 + fn, i); break; case e32: - val = STATE.VU.elt<uint32_t>(vs3 + fn, i); + val = p->VU.elt<uint32_t>(vs3 + fn, i); break; defaualt: - val = STATE.VU.elt<uint64_t>(vs3 + fn, i); + val = p->VU.elt<uint64_t>(vs3 + fn, i); break; } MMU.store_uint16(baseAddr + index + fn * 2, val); } } -STATE.VU.vstart = 0; +p->VU.vstart = 0; diff --git a/riscv/insns/vsxw_v.h b/riscv/insns/vsxw_v.h index db198aa..b0b594f 100644 --- a/riscv/insns/vsxw_v.h +++ b/riscv/insns/vsxw_v.h @@ -1,26 +1,26 @@ // vsxw.v and vsxseg[2-8]w.v -require(STATE.VU.vsew >= e32); +require(p->VU.vsew >= e32); reg_t nf = insn.v_nf() + 1; -require((nf >= 2 && STATE.VU.vlmul == 1) || nf == 1); -reg_t vl = STATE.VU.vl; +require((nf >= 2 && p->VU.vlmul == 1) || nf == 1); +reg_t vl = p->VU.vl; reg_t baseAddr = RS1; reg_t stride = insn.rs2(); reg_t vs3 = insn.rd(); -for (reg_t i = STATE.VU.vstart; i < vl; ++i) { +for (reg_t i = p->VU.vstart; i < vl; ++i) { V_LOOP_ELEMENT_SKIP; - reg_t index = STATE.VU.elt<int32_t>(stride, i); + reg_t index = p->VU.elt<int32_t>(stride, i); for (reg_t fn = 0; fn < nf; ++fn) { uint32_t val = 0; - switch (STATE.VU.vsew) { + switch (p->VU.vsew) { case e32: - val = STATE.VU.elt<uint32_t>(vs3 + fn, i); + val = p->VU.elt<uint32_t>(vs3 + fn, i); break; defaualt: - val = STATE.VU.elt<uint64_t>(vs3 + fn, i); + val = p->VU.elt<uint64_t>(vs3 + fn, i); break; } MMU.store_uint32(baseAddr + index + fn * 4, val); } } -STATE.VU.vstart = 0; +p->VU.vstart = 0; diff --git a/riscv/insns/vwmulsu_vv.h b/riscv/insns/vwmulsu_vv.h index fe492cd..7602988 100644 --- a/riscv/insns/vwmulsu_vv.h +++ b/riscv/insns/vwmulsu_vv.h @@ -2,15 +2,15 @@ V_WIDE_CHECK; VI_VV_LOOP ({ - switch(STATE.VU.vsew) { + switch(p->VU.vsew) { case e8: - STATE.VU.elt<uint16_t>(rd_num, i) = (int16_t)(int8_t)vs2 * (int16_t)(uint8_t)vs1; + p->VU.elt<uint16_t>(rd_num, i) = (int16_t)(int8_t)vs2 * (int16_t)(uint8_t)vs1; break; case e16: - STATE.VU.elt<uint32_t>(rd_num, i) = (int32_t)(int16_t)vs2 * (int32_t)(uint16_t)vs1; + p->VU.elt<uint32_t>(rd_num, i) = (int32_t)(int16_t)vs2 * (int32_t)(uint16_t)vs1; break; default: - STATE.VU.elt<uint64_t>(rd_num, i) = (int64_t)(int32_t)vs2 * (int64_t)(uint32_t)vs1; + p->VU.elt<uint64_t>(rd_num, i) = (int64_t)(int32_t)vs2 * (int64_t)(uint32_t)vs1; break; } }) diff --git a/riscv/insns/vwmulsu_vx.h b/riscv/insns/vwmulsu_vx.h index 078bc5b..e0348ce 100644 --- a/riscv/insns/vwmulsu_vx.h +++ b/riscv/insns/vwmulsu_vx.h @@ -2,15 +2,15 @@ V_WIDE_CHECK; VI_VX_LOOP ({ - switch(STATE.VU.vsew) { + switch(p->VU.vsew) { case e8: - STATE.VU.elt<uint16_t>(rd_num, i) = (int16_t)(int8_t)vs2 * (int16_t)(uint8_t)rs1; + p->VU.elt<uint16_t>(rd_num, i) = (int16_t)(int8_t)vs2 * (int16_t)(uint8_t)rs1; break; case e16: - STATE.VU.elt<uint32_t>(rd_num, i) = (int32_t)(int16_t)vs2 * (int32_t)(uint16_t)rs1; + p->VU.elt<uint32_t>(rd_num, i) = (int32_t)(int16_t)vs2 * (int32_t)(uint16_t)rs1; break; default: - STATE.VU.elt<uint64_t>(rd_num, i) = (int64_t)(int32_t)vs2 * (int64_t)(uint32_t)rs1; + p->VU.elt<uint64_t>(rd_num, i) = (int64_t)(int32_t)vs2 * (int64_t)(uint32_t)rs1; break; } }) |