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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-04-27 11:11:46 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-04-27 11:12:13 -0700 |
| commit | 9cff83b2072bb1b6ad65fac4484bfd3d2deb62c6 (patch) | |
| tree | cbd9adcac5467cd5a40e036e8ad34bf9b32b3dbc /riscv/insns | |
| parent | 8f5e8712b637198bff7a58aa3bb74470417809c9 (diff) | |
| download | spike-9cff83b2072bb1b6ad65fac4484bfd3d2deb62c6.zip spike-9cff83b2072bb1b6ad65fac4484bfd3d2deb62c6.tar.gz spike-9cff83b2072bb1b6ad65fac4484bfd3d2deb62c6.tar.bz2 | |
rvv: commitlog: fix comparision dst information
Comparison only writes one vector register
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/insns')
| -rw-r--r-- | riscv/insns/vmsgtu_vi.h | 2 | ||||
| -rw-r--r-- | riscv/insns/vmsleu_vi.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/riscv/insns/vmsgtu_vi.h b/riscv/insns/vmsgtu_vi.h index ee47e50..be28fee 100644 --- a/riscv/insns/vmsgtu_vi.h +++ b/riscv/insns/vmsgtu_vi.h @@ -1,4 +1,4 @@ -// vsgtu.vi vd, vd2, simm5 +// vmsgtu.vi vd, vd2, simm5 VI_VI_ULOOP_CMP ({ res = vs2 > (insn.v_simm5() & (UINT64_MAX >> (64 - P.VU.vsew))); diff --git a/riscv/insns/vmsleu_vi.h b/riscv/insns/vmsleu_vi.h index d11ff6a..0e66b78 100644 --- a/riscv/insns/vmsleu_vi.h +++ b/riscv/insns/vmsleu_vi.h @@ -1,4 +1,4 @@ -// vsleu.vi vd, vs2, simm5 +// vmsleu.vi vd, vs2, simm5 VI_VI_ULOOP_CMP ({ res = vs2 <= (insn.v_simm5() & (UINT64_MAX >> (64 - P.VU.vsew))); |