[sim] add vector traps to vector instructions

43 files changed, 43 insertions, 0 deletions

diff --git a/riscv/insns/fld_v.h b/riscv/insns/fld_v.h
index c2d5072..9b40470 100644
--- a/riscv/insns/fld_v.h
+++ b/riscv/insns/fld_v.h
@@ -1,2 +1,3 @@
+require_vector;
 require_fp;
 VEC_LOAD(FRD, load_int64, 8);
diff --git a/riscv/insns/fldst_v.h b/riscv/insns/fldst_v.h
index 60f9965..fa9b32d 100644
--- a/riscv/insns/fldst_v.h
+++ b/riscv/insns/fldst_v.h
@@ -1,2 +1,3 @@
+require_vector;
 require_fp;
 VEC_LOAD(FRD, load_int64, RS2);
diff --git a/riscv/insns/flw_v.h b/riscv/insns/flw_v.h
index 1e54f7e..75fdd04 100644
--- a/riscv/insns/flw_v.h
+++ b/riscv/insns/flw_v.h
@@ -1,2 +1,3 @@
+require_vector;
 require_fp;
 VEC_LOAD(FRD, load_int32, 4);
diff --git a/riscv/insns/flwst_v.h b/riscv/insns/flwst_v.h
index d11c632..716c818 100644
--- a/riscv/insns/flwst_v.h
+++ b/riscv/insns/flwst_v.h
@@ -1,2 +1,3 @@
+require_vector;
 require_fp;
 VEC_LOAD(FRD, load_int32, RS2);
diff --git a/riscv/insns/fmov_su.h b/riscv/insns/fmov_su.h
index 65d00ba..20fa123 100644
--- a/riscv/insns/fmov_su.h
+++ b/riscv/insns/fmov_su.h
@@ -1,3 +1,4 @@
+require_vector;
 require_fp;
 demand(0 <= RS2 && RS2 < MAX_UTS, "ut not in range!");
 UT_FRD(RS2) = FRS1;
diff --git a/riscv/insns/fmov_sv.h b/riscv/insns/fmov_sv.h
index b689ed8..a9aa876 100644
--- a/riscv/insns/fmov_sv.h
+++ b/riscv/insns/fmov_sv.h
@@ -1,3 +1,4 @@
+require_vector;
 require_fp;
 UT_LOOP_START
   UT_LOOP_FRD = FRS1;
diff --git a/riscv/insns/fmov_us.h b/riscv/insns/fmov_us.h
index 4052739..6f56b25 100644
--- a/riscv/insns/fmov_us.h
+++ b/riscv/insns/fmov_us.h
@@ -1,3 +1,4 @@
+require_vector;
 require_fp;
 demand(0 <= RS2 && RS2 < MAX_UTS, "ut not in range");
 FRD = UT_FRS1(RS2);
diff --git a/riscv/insns/fmov_vv.h b/riscv/insns/fmov_vv.h
index 28269fd..279da21 100644
--- a/riscv/insns/fmov_vv.h
+++ b/riscv/insns/fmov_vv.h
@@ -1,3 +1,4 @@
+require_vector;
 require_fp;
 UT_LOOP_START
   UT_LOOP_FRD = UT_LOOP_FRS1;
diff --git a/riscv/insns/fsd_v.h b/riscv/insns/fsd_v.h
index 28871d5..f619fc8 100644
--- a/riscv/insns/fsd_v.h
+++ b/riscv/insns/fsd_v.h
@@ -1,2 +1,3 @@
+require_vector;
 require_fp;
 VEC_STORE(FRD, store_uint64, 8);
diff --git a/riscv/insns/fsdst_v.h b/riscv/insns/fsdst_v.h
index 9a0b83d..b3bb260 100644
--- a/riscv/insns/fsdst_v.h
+++ b/riscv/insns/fsdst_v.h
@@ -1,2 +1,3 @@
+require_vector;
 require_fp;
 VEC_STORE(FRD, store_uint64, RS2);
diff --git a/riscv/insns/fsw_v.h b/riscv/insns/fsw_v.h
index 6cb3580..3fe3d3f 100644
--- a/riscv/insns/fsw_v.h
+++ b/riscv/insns/fsw_v.h
@@ -1,2 +1,3 @@
+require_vector;
 require_fp;
 VEC_STORE(FRD, store_uint32, 4);
diff --git a/riscv/insns/fswst_v.h b/riscv/insns/fswst_v.h
index 9991e2c..9cef9b0 100644
--- a/riscv/insns/fswst_v.h
+++ b/riscv/insns/fswst_v.h
@@ -1,2 +1,3 @@
+require_vector;
 require_fp;
 VEC_STORE(FRD, store_uint32, RS2);
diff --git a/riscv/insns/lb_v.h b/riscv/insns/lb_v.h
index 5246d98..618380a 100644
--- a/riscv/insns/lb_v.h
+++ b/riscv/insns/lb_v.h
@@ -1 +1,2 @@
+require_vector;
 VEC_LOAD(RD, load_int8, 1);
diff --git a/riscv/insns/lbst_v.h b/riscv/insns/lbst_v.h
index 91c8c3a..219d90e 100644
--- a/riscv/insns/lbst_v.h
+++ b/riscv/insns/lbst_v.h
@@ -1 +1,2 @@
+require_vector;
 VEC_LOAD(RD, load_int8, RS2);
diff --git a/riscv/insns/lbu_v.h b/riscv/insns/lbu_v.h
index 72d9af2..f92c8b5 100644
--- a/riscv/insns/lbu_v.h
+++ b/riscv/insns/lbu_v.h
@@ -1 +1,2 @@
+require_vector;
 VEC_LOAD(RD, load_uint8, 1);
diff --git a/riscv/insns/lbust_v.h b/riscv/insns/lbust_v.h
index 81ad75f..09faa29 100644
--- a/riscv/insns/lbust_v.h
+++ b/riscv/insns/lbust_v.h
@@ -1 +1,2 @@
+require_vector;
 VEC_LOAD(RD, load_uint8, RS2);
diff --git a/riscv/insns/ld_v.h b/riscv/insns/ld_v.h
index 124f9be..fb7a3c5 100644
--- a/riscv/insns/ld_v.h
+++ b/riscv/insns/ld_v.h
@@ -1,2 +1,3 @@
+require_vector;
 require_xpr64;
 VEC_LOAD(RD, load_int64, 8);
diff --git a/riscv/insns/ldst_v.h b/riscv/insns/ldst_v.h
index 84aa0fc..5e5de9c 100644
--- a/riscv/insns/ldst_v.h
+++ b/riscv/insns/ldst_v.h
@@ -1,2 +1,3 @@
+require_vector;
 require_xpr64;
 VEC_LOAD(RD, load_int64, RS2);
diff --git a/riscv/insns/lh_v.h b/riscv/insns/lh_v.h
index 2943110..269c2a8 100644
--- a/riscv/insns/lh_v.h
+++ b/riscv/insns/lh_v.h
@@ -1 +1,2 @@
+require_vector;
 VEC_LOAD(RD, load_int16, 2);
diff --git a/riscv/insns/lhst_v.h b/riscv/insns/lhst_v.h
index 1bcd364..af6b5b5 100644
--- a/riscv/insns/lhst_v.h
+++ b/riscv/insns/lhst_v.h
@@ -1 +1,2 @@
+require_vector;
 VEC_LOAD(RD, load_int16, RS2);
diff --git a/riscv/insns/lhu_v.h b/riscv/insns/lhu_v.h
index b932aef..7a2019d 100644
--- a/riscv/insns/lhu_v.h
+++ b/riscv/insns/lhu_v.h
@@ -1 +1,2 @@
+require_vector;
 VEC_LOAD(RD, load_uint16, 2);
diff --git a/riscv/insns/lhust_v.h b/riscv/insns/lhust_v.h
index d111428..0fe8452 100644
--- a/riscv/insns/lhust_v.h
+++ b/riscv/insns/lhust_v.h
@@ -1 +1,2 @@
+require_vector;
 VEC_LOAD(RD, load_uint16, RS2);
diff --git a/riscv/insns/lw_v.h b/riscv/insns/lw_v.h
index 980a164..6e35911 100644
--- a/riscv/insns/lw_v.h
+++ b/riscv/insns/lw_v.h
@@ -1 +1,2 @@
+require_vector;
 VEC_LOAD(RD, load_int32, 4);
diff --git a/riscv/insns/lwst_v.h b/riscv/insns/lwst_v.h
index 735a620..5375dc0 100644
--- a/riscv/insns/lwst_v.h
+++ b/riscv/insns/lwst_v.h
@@ -1 +1,2 @@
+require_vector;
 VEC_LOAD(RD, load_int32, RS2);
diff --git a/riscv/insns/lwu_v.h b/riscv/insns/lwu_v.h
index b1cdf37..4fa1489 100644
--- a/riscv/insns/lwu_v.h
+++ b/riscv/insns/lwu_v.h
@@ -1 +1,2 @@
+require_vector;
 VEC_LOAD(RD, load_uint32, 4);
diff --git a/riscv/insns/lwust_v.h b/riscv/insns/lwust_v.h
index 7e0c006..328e23f 100644
--- a/riscv/insns/lwust_v.h
+++ b/riscv/insns/lwust_v.h
@@ -1 +1,2 @@
+require_vector;
 VEC_LOAD(RD, load_uint32, RS2);
diff --git a/riscv/insns/mov_su.h b/riscv/insns/mov_su.h
index b55ab2f..7b7cae1 100644
--- a/riscv/insns/mov_su.h
+++ b/riscv/insns/mov_su.h
@@ -1,2 +1,3 @@
+require_vector;
 demand(0 <= RS2 && RS2 < MAX_UTS, "ut not in range!");
 UT_RD(RS2) = RS1;
diff --git a/riscv/insns/mov_sv.h b/riscv/insns/mov_sv.h
index 03bb29d..c6f4c2c 100644
--- a/riscv/insns/mov_sv.h
+++ b/riscv/insns/mov_sv.h
@@ -1,3 +1,4 @@
+require_vector;
 UT_LOOP_START
   UT_LOOP_RD = RS1;
 UT_LOOP_END
diff --git a/riscv/insns/mov_us.h b/riscv/insns/mov_us.h
index 05699a8..a69e388 100644
--- a/riscv/insns/mov_us.h
+++ b/riscv/insns/mov_us.h
@@ -1,2 +1,3 @@
+require_vector;
 demand(0 <= RS2 && RS2 < MAX_UTS, "ut not in range");
 RD = UT_RS1(RS2);
diff --git a/riscv/insns/mov_vv.h b/riscv/insns/mov_vv.h
index 2a1b0b6..91d63d4 100644
--- a/riscv/insns/mov_vv.h
+++ b/riscv/insns/mov_vv.h
@@ -1,3 +1,4 @@
+require_vector;
 UT_LOOP_START
   UT_LOOP_RD = UT_LOOP_RS1;
 UT_LOOP_END
diff --git a/riscv/insns/sb_v.h b/riscv/insns/sb_v.h
index 81e3513..c3d5b9d 100644
--- a/riscv/insns/sb_v.h
+++ b/riscv/insns/sb_v.h
@@ -1 +1,2 @@
+require_vector;
 VEC_STORE(RD, store_uint8, 1);
diff --git a/riscv/insns/sbst_v.h b/riscv/insns/sbst_v.h
index 2d7c59b..b83cc50 100644
--- a/riscv/insns/sbst_v.h
+++ b/riscv/insns/sbst_v.h
@@ -1 +1,2 @@
+require_vector;
 VEC_STORE(RD, store_uint8, RS2);
diff --git a/riscv/insns/sd_v.h b/riscv/insns/sd_v.h
index 330e1b0..9c02069 100644
--- a/riscv/insns/sd_v.h
+++ b/riscv/insns/sd_v.h
@@ -1,2 +1,3 @@
+require_vector;
 require_xpr64;
 VEC_STORE(RD, store_uint64, 8);
diff --git a/riscv/insns/sdst_v.h b/riscv/insns/sdst_v.h
index d3e74d3..26868d2 100644
--- a/riscv/insns/sdst_v.h
+++ b/riscv/insns/sdst_v.h
@@ -1,2 +1,3 @@
+require_vector;
 require_xpr64;
 VEC_STORE(RD, store_uint64, RS2);
diff --git a/riscv/insns/setvl.h b/riscv/insns/setvl.h
index 5b611db..c2212ff 100644
--- a/riscv/insns/setvl.h
+++ b/riscv/insns/setvl.h
@@ -1,2 +1,3 @@
+require_vector;
 setvl(RS1);
 RD = VL;
diff --git a/riscv/insns/sh_v.h b/riscv/insns/sh_v.h
index fdfe6fe..623eda8 100644
--- a/riscv/insns/sh_v.h
+++ b/riscv/insns/sh_v.h
@@ -1 +1,2 @@
+require_vector;
 VEC_STORE(RD, store_uint16, 2);
diff --git a/riscv/insns/shst_v.h b/riscv/insns/shst_v.h
index 4f4044c..3904331 100644
--- a/riscv/insns/shst_v.h
+++ b/riscv/insns/shst_v.h
@@ -1 +1,2 @@
+require_vector;
 VEC_STORE(RD, store_uint16, RS2);
diff --git a/riscv/insns/stop.h b/riscv/insns/stop.h
index cbf69dc..791a82c 100644
--- a/riscv/insns/stop.h
+++ b/riscv/insns/stop.h
@@ -1,2 +1,3 @@
+require_vector;
 utmode = false;
 throw vt_command_stop;
diff --git a/riscv/insns/sw_v.h b/riscv/insns/sw_v.h
index 276da95..662d4e3 100644
--- a/riscv/insns/sw_v.h
+++ b/riscv/insns/sw_v.h
@@ -1 +1,2 @@
+require_vector;
 VEC_STORE(RD, store_uint32, 4);
diff --git a/riscv/insns/swst_v.h b/riscv/insns/swst_v.h
index 08b198c..8f05953 100644
--- a/riscv/insns/swst_v.h
+++ b/riscv/insns/swst_v.h
@@ -1 +1,2 @@
+require_vector;
 VEC_STORE(RD, store_uint32, RS2);
diff --git a/riscv/insns/utidx.h b/riscv/insns/utidx.h
index 70336ac..b3c944c 100644
--- a/riscv/insns/utidx.h
+++ b/riscv/insns/utidx.h
@@ -1 +1,2 @@
+require_vector;
 RD = utidx;
diff --git a/riscv/insns/vcfgivl.h b/riscv/insns/vcfgivl.h
index c870f67..0ded9f8 100644
--- a/riscv/insns/vcfgivl.h
+++ b/riscv/insns/vcfgivl.h
@@ -1,3 +1,4 @@
+require_vector;
 nxpr_use = SIMM & 0x3f;
 nfpr_use = (SIMM >> 6) & 0x3f;
 vcfg();
diff --git a/riscv/insns/vf.h b/riscv/insns/vf.h
index eff542c..c3a43cf 100644
--- a/riscv/insns/vf.h
+++ b/riscv/insns/vf.h
@@ -1,3 +1,4 @@
+require_vector;
 for (int i=0; i<VL; i++)
 {
   uts[i]->pc = RS1+SIMM;