rvv: fix floating comparison for fp16

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

9 files changed, 27 insertions, 0 deletions

diff --git a/riscv/insns/vfwadd_vf.h b/riscv/insns/vfwadd_vf.h
index ecac202..b824900 100644
--- a/riscv/insns/vfwadd_vf.h
+++ b/riscv/insns/vfwadd_vf.h
@@ -1,5 +1,8 @@
 // vfwadd.vf vd, vs2, rs1
 VI_VFP_VF_LOOP_WIDE
 ({
+  vd = f32_add(vs2, rs1);
+},
+{
   vd = f64_add(vs2, rs1);
 })
diff --git a/riscv/insns/vfwadd_wf.h b/riscv/insns/vfwadd_wf.h
index eb38d0d..021b17f 100644
--- a/riscv/insns/vfwadd_wf.h
+++ b/riscv/insns/vfwadd_wf.h
@@ -1,5 +1,8 @@
 // vfwadd.wf vd, vs2, vs1
 VI_VFP_WF_LOOP_WIDE
 ({
+  vd = f32_add(vs2, rs1);
+},
+{
   vd = f64_add(vs2, rs1);
 })
diff --git a/riscv/insns/vfwmacc_vf.h b/riscv/insns/vfwmacc_vf.h
index 6ee011e..441fa0a 100644
--- a/riscv/insns/vfwmacc_vf.h
+++ b/riscv/insns/vfwmacc_vf.h
@@ -1,5 +1,8 @@
 // vfwmacc.vf vd, vs2, rs1
 VI_VFP_VF_LOOP_WIDE
 ({
+  vd = f32_mulAdd(rs1, vs2, vd);
+},
+{
   vd = f64_mulAdd(rs1, vs2, vd);
 })
diff --git a/riscv/insns/vfwmsac_vf.h b/riscv/insns/vfwmsac_vf.h
index ea8f050..18010ff 100644
--- a/riscv/insns/vfwmsac_vf.h
+++ b/riscv/insns/vfwmsac_vf.h
@@ -1,5 +1,8 @@
 // vfwmsac.vf vd, vs2, rs1
 VI_VFP_VF_LOOP_WIDE
 ({
+  vd = f32_mulAdd(rs1, vs2, f32(vd.v ^ F32_SIGN));
+},
+{
   vd = f64_mulAdd(rs1, vs2, f64(vd.v ^ F64_SIGN));
 })
diff --git a/riscv/insns/vfwmul_vf.h b/riscv/insns/vfwmul_vf.h
index 884e66f..2bb543f 100644
--- a/riscv/insns/vfwmul_vf.h
+++ b/riscv/insns/vfwmul_vf.h
@@ -1,5 +1,8 @@
 // vfwmul.vf vd, vs2, rs1
 VI_VFP_VF_LOOP_WIDE
 ({
+  vd = f32_mul(vs2, rs1);
+},
+{
   vd = f64_mul(vs2, rs1);
 })
diff --git a/riscv/insns/vfwnmacc_vf.h b/riscv/insns/vfwnmacc_vf.h
index bccc24f..038bda0 100644
--- a/riscv/insns/vfwnmacc_vf.h
+++ b/riscv/insns/vfwnmacc_vf.h
@@ -1,5 +1,8 @@
 // vfwnmacc.vf vd, vs2, rs1
 VI_VFP_VF_LOOP_WIDE
 ({
+  vd = f32_mulAdd(f32(rs1.v ^ F32_SIGN), vs2, f32(vd.v ^ F32_SIGN));
+},
+{
   vd = f64_mulAdd(f64(rs1.v ^ F64_SIGN), vs2, f64(vd.v ^ F64_SIGN));
 })
diff --git a/riscv/insns/vfwnmsac_vf.h b/riscv/insns/vfwnmsac_vf.h
index 32ef624..1e288e1 100644
--- a/riscv/insns/vfwnmsac_vf.h
+++ b/riscv/insns/vfwnmsac_vf.h
@@ -1,5 +1,8 @@
 // vfwnmacc.vf vd, vs2, rs1
 VI_VFP_VF_LOOP_WIDE
 ({
+  vd = f32_mulAdd(f32(rs1.v ^ F32_SIGN), vs2, vd);
+},
+{
   vd = f64_mulAdd(f64(rs1.v ^ F64_SIGN), vs2, vd);
 })
diff --git a/riscv/insns/vfwsub_vf.h b/riscv/insns/vfwsub_vf.h
index 1d20c38..8c37688 100644
--- a/riscv/insns/vfwsub_vf.h
+++ b/riscv/insns/vfwsub_vf.h
@@ -1,5 +1,8 @@
 // vfwsub.vf vd, vs2, rs1
 VI_VFP_VF_LOOP_WIDE
 ({
+  vd = f32_sub(vs2, rs1);
+},
+{
   vd = f64_sub(vs2, rs1);
 })
diff --git a/riscv/insns/vfwsub_wf.h b/riscv/insns/vfwsub_wf.h
index fa3d747..f6f47ca 100644
--- a/riscv/insns/vfwsub_wf.h
+++ b/riscv/insns/vfwsub_wf.h
@@ -1,5 +1,8 @@
 // vfwsub.wf vd, vs2, rs1
 VI_VFP_WF_LOOP_WIDE
 ({
+  vd = f32_sub(vs2, rs1);
+},
+{
   vd = f64_sub(vs2, rs1);
 })