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author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-04-21 21:29:24 -0700 |
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committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-04-21 21:30:48 -0700 |
commit | 056cbfd7fa5a47191812dfef9aeb3b63159e1f22 (patch) | |
tree | 4644bb6ddb5fe90c032a8b59183b02f75284ae5e /riscv/insns | |
parent | b76e7480fe465ca51e7a8d2e55f53104f4e61c58 (diff) | |
download | spike-056cbfd7fa5a47191812dfef9aeb3b63159e1f22.zip spike-056cbfd7fa5a47191812dfef9aeb3b63159e1f22.tar.gz spike-056cbfd7fa5a47191812dfef9aeb3b63159e1f22.tar.bz2 |
rvv: fix vfmv for fp16
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/insns')
-rw-r--r-- | riscv/insns/vfmv_f_s.h | 25 | ||||
-rw-r--r-- | riscv/insns/vfmv_s_f.h | 16 | ||||
-rw-r--r-- | riscv/insns/vfmv_v_f.h | 8 |
3 files changed, 36 insertions, 13 deletions
diff --git a/riscv/insns/vfmv_f_s.h b/riscv/insns/vfmv_f_s.h index 586b80e..2f82ce8 100644 --- a/riscv/insns/vfmv_f_s.h +++ b/riscv/insns/vfmv_f_s.h @@ -1,24 +1,31 @@ // vfmv_f_s: rd = vs2[0] (rs1=0) require_vector; require_fp; -require_extension('F'); -require(P.VU.vsew == e32 || P.VU.vsew == e64); +require((P.VU.vsew == e16 && p->supports_extension(EXT_ZFH)) || + (P.VU.vsew == e32 && p->supports_extension('F')) || + (P.VU.vsew == e64 && p->supports_extension('D'))); reg_t rs2_num = insn.rs2(); uint64_t vs2_0 = 0; const reg_t sew = P.VU.vsew; switch(sew) { -case e32: - vs2_0 = P.VU.elt<uint32_t>(rs2_num, 0); - break; -default: - vs2_0 = P.VU.elt<uint64_t>(rs2_num, 0); - break; + case e16: + vs2_0 = P.VU.elt<uint16_t>(rs2_num, 0); + break; + case e32: + vs2_0 = P.VU.elt<uint32_t>(rs2_num, 0); + break; + case e64: + vs2_0 = P.VU.elt<uint64_t>(rs2_num, 0); + break; + default: + require(0); + break; } // nan_extened if (FLEN > sew) { - vs2_0 = vs2_0 | ~((uint64_t(1) << sew) - 1); + vs2_0 = vs2_0 | (UINT64_MAX << sew); } if (FLEN == 64) { diff --git a/riscv/insns/vfmv_s_f.h b/riscv/insns/vfmv_s_f.h index 84c5a3f..d29e245 100644 --- a/riscv/insns/vfmv_s_f.h +++ b/riscv/insns/vfmv_s_f.h @@ -1,21 +1,29 @@ // vfmv_s_f: vd[0] = rs1 (vs2=0) require_vector; require_fp; -require_extension('F'); -require(P.VU.vsew >= e32 && P.VU.vsew <= 64); +require((P.VU.vsew == e16 && p->supports_extension(EXT_ZFH)) || + (P.VU.vsew == e32 && p->supports_extension('F')) || + (P.VU.vsew == e64 && p->supports_extension('D'))); + reg_t vl = P.VU.vl; if (vl > 0 && P.VU.vstart < vl) { reg_t rd_num = insn.rd(); switch(P.VU.vsew) { - case 32: + case e16: + if (FLEN == 64) + P.VU.elt<uint16_t>(rd_num, 0, true) = f64(FRS1).v; + else + P.VU.elt<uint16_t>(rd_num, 0, true) = f32(FRS1).v; + break; + case e32: if (FLEN == 64) P.VU.elt<uint32_t>(rd_num, 0, true) = f64(FRS1).v; else P.VU.elt<uint32_t>(rd_num, 0, true) = f32(FRS1).v; break; - case 64: + case e64: if (FLEN == 64) P.VU.elt<uint64_t>(rd_num, 0, true) = f64(FRS1).v; else diff --git a/riscv/insns/vfmv_v_f.h b/riscv/insns/vfmv_v_f.h index f85a26a..e4cdec4 100644 --- a/riscv/insns/vfmv_v_f.h +++ b/riscv/insns/vfmv_v_f.h @@ -2,6 +2,14 @@ require((insn.rd() & (P.VU.vlmul - 1)) == 0); VI_VFP_COMMON switch(P.VU.vsew) { + case e16: + for (reg_t i=P.VU.vstart; i<vl; ++i) { + auto &vd = P.VU.elt<float16_t>(rd_num, i, true); + auto rs1 = f16(READ_FREG(rs1_num)); + + vd = rs1; + } + break; case e32: for (reg_t i=P.VU.vstart; i<vl; ++i) { auto &vd = P.VU.elt<float32_t>(rd_num, i, true); |