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author | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-11-19 00:05:02 -0800 |
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committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-12-20 09:58:46 -0800 |
commit | fd132e6214751c70a9aa332b26edbbba983561de (patch) | |
tree | c2874245277571f9eeb99106a29b04f0477720d2 /riscv/insns | |
parent | 08343bba3bd9f59cefa11ed59724908dfbe84967 (diff) | |
download | spike-fd132e6214751c70a9aa332b26edbbba983561de.zip spike-fd132e6214751c70a9aa332b26edbbba983561de.tar.gz spike-fd132e6214751c70a9aa332b26edbbba983561de.tar.bz2 |
rvv: rename vfncvt suffix and add rod rouding type
1. vfncvt*.v -> vfncvt*.w
2. add vfncvt.rod.f.f.w
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/insns')
-rw-r--r-- | riscv/insns/vfncvt_f_f_w.h (renamed from riscv/insns/vfncvt_f_f_v.h) | 2 | ||||
-rw-r--r-- | riscv/insns/vfncvt_f_x_w.h (renamed from riscv/insns/vfncvt_f_x_v.h) | 2 | ||||
-rw-r--r-- | riscv/insns/vfncvt_f_xu_w.h (renamed from riscv/insns/vfncvt_f_xu_v.h) | 2 | ||||
-rw-r--r-- | riscv/insns/vfncvt_rod_f_f_w.h | 7 | ||||
-rw-r--r-- | riscv/insns/vfncvt_x_f_w.h (renamed from riscv/insns/vfncvt_x_f_v.h) | 0 | ||||
-rw-r--r-- | riscv/insns/vfncvt_xu_f_w.h (renamed from riscv/insns/vfncvt_xu_f_v.h) | 0 |
6 files changed, 10 insertions, 3 deletions
diff --git a/riscv/insns/vfncvt_f_f_v.h b/riscv/insns/vfncvt_f_f_w.h index b35cd60..42c18c7 100644 --- a/riscv/insns/vfncvt_f_f_v.h +++ b/riscv/insns/vfncvt_f_f_w.h @@ -1,6 +1,6 @@ // vfncvt.f.f.v vd, vs2, vm +VI_CHECK_SD; VI_VFP_LOOP_BASE - VI_CHECK_SD; auto vs2 = P.VU.elt<float64_t>(rs2_num, i); P.VU.elt<float32_t>(rd_num, i) = f64_to_f32(vs2); VI_VFP_LOOP_END diff --git a/riscv/insns/vfncvt_f_x_v.h b/riscv/insns/vfncvt_f_x_w.h index 69bdba8..80ebe00 100644 --- a/riscv/insns/vfncvt_f_x_v.h +++ b/riscv/insns/vfncvt_f_x_w.h @@ -1,6 +1,6 @@ // vfncvt.f.x.v vd, vs2, vm +VI_CHECK_SD; VI_VFP_LOOP_BASE - VI_CHECK_SD; auto vs2 = P.VU.elt<int64_t>(rs2_num, i); P.VU.elt<float32_t>(rd_num, i) = i64_to_f32(vs2); VI_VFP_LOOP_END diff --git a/riscv/insns/vfncvt_f_xu_v.h b/riscv/insns/vfncvt_f_xu_w.h index 6f37734..013f57c 100644 --- a/riscv/insns/vfncvt_f_xu_v.h +++ b/riscv/insns/vfncvt_f_xu_w.h @@ -1,6 +1,6 @@ // vfncvt.f.xu.v vd, vs2, vm +VI_CHECK_SD; VI_VFP_LOOP_BASE - VI_CHECK_SD; auto vs2 = P.VU.elt<uint64_t>(rs2_num, i); P.VU.elt<float32_t>(rd_num, i) = ui64_to_f32(vs2); VI_VFP_LOOP_END diff --git a/riscv/insns/vfncvt_rod_f_f_w.h b/riscv/insns/vfncvt_rod_f_f_w.h new file mode 100644 index 0000000..77a3873 --- /dev/null +++ b/riscv/insns/vfncvt_rod_f_f_w.h @@ -0,0 +1,7 @@ +// vfncvt.f.f.v vd, vs2, vm +VI_CHECK_SD; +VI_VFP_LOOP_BASE + softfloat_roundingMode = softfloat_round_odd; + auto vs2 = P.VU.elt<float64_t>(rs2_num, i); + P.VU.elt<float32_t>(rd_num, i) = f64_to_f32(vs2); +VI_VFP_LOOP_END diff --git a/riscv/insns/vfncvt_x_f_v.h b/riscv/insns/vfncvt_x_f_w.h index 8985f1b..8985f1b 100644 --- a/riscv/insns/vfncvt_x_f_v.h +++ b/riscv/insns/vfncvt_x_f_w.h diff --git a/riscv/insns/vfncvt_xu_f_v.h b/riscv/insns/vfncvt_xu_f_w.h index 2db8d82..2db8d82 100644 --- a/riscv/insns/vfncvt_xu_f_v.h +++ b/riscv/insns/vfncvt_xu_f_w.h |