Support setting ISA/subsets with --isa flag

Default is RV64IMAFDC.  Can do things like

  --isa=RV32 (which implies IMAFDC)
  --isa=IM (which implies RV64)
  --isa=RV64IMAFDXhwacha

152 files changed, 119 insertions, 22 deletions

diff --git a/riscv/insns/amoadd_d.h b/riscv/insns/amoadd_d.h
index c6bacaf..9c7c124 100644
--- a/riscv/insns/amoadd_d.h
+++ b/riscv/insns/amoadd_d.h
@@ -1,3 +1,4 @@
+require_extension('A');
 require_rv64;
 reg_t v = MMU.load_uint64(RS1);
 MMU.store_uint64(RS1, RS2 + v);
diff --git a/riscv/insns/amoadd_w.h b/riscv/insns/amoadd_w.h
index 8eb9e2b..7ac59b0 100644
--- a/riscv/insns/amoadd_w.h
+++ b/riscv/insns/amoadd_w.h
@@ -1,3 +1,4 @@
+require_extension('A');
 reg_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, RS2 + v);
 WRITE_RD(v);
diff --git a/riscv/insns/amoand_d.h b/riscv/insns/amoand_d.h
index d896ec1..7aa6386 100644
--- a/riscv/insns/amoand_d.h
+++ b/riscv/insns/amoand_d.h
@@ -1,3 +1,4 @@
+require_extension('A');
 require_rv64;
 reg_t v = MMU.load_uint64(RS1);
 MMU.store_uint64(RS1, RS2 & v);
diff --git a/riscv/insns/amoand_w.h b/riscv/insns/amoand_w.h
index 32ea7f7..7db2160 100644
--- a/riscv/insns/amoand_w.h
+++ b/riscv/insns/amoand_w.h
@@ -1,3 +1,4 @@
+require_extension('A');
 reg_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, RS2 & v);
 WRITE_RD(v);
diff --git a/riscv/insns/amomax_d.h b/riscv/insns/amomax_d.h
index 0a66214..0f6da18 100644
--- a/riscv/insns/amomax_d.h
+++ b/riscv/insns/amomax_d.h
@@ -1,3 +1,4 @@
+require_extension('A');
 require_rv64;
 sreg_t v = MMU.load_int64(RS1);
 MMU.store_uint64(RS1, std::max(sreg_t(RS2),v));
diff --git a/riscv/insns/amomax_w.h b/riscv/insns/amomax_w.h
index a255116..8c9222b 100644
--- a/riscv/insns/amomax_w.h
+++ b/riscv/insns/amomax_w.h
@@ -1,3 +1,4 @@
+require_extension('A');
 int32_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, std::max(int32_t(RS2),v));
 WRITE_RD(v);
diff --git a/riscv/insns/amomaxu_d.h b/riscv/insns/amomaxu_d.h
index dbdb1d2..6760f91 100644
--- a/riscv/insns/amomaxu_d.h
+++ b/riscv/insns/amomaxu_d.h
@@ -1,3 +1,4 @@
+require_extension('A');
 require_rv64;
 reg_t v = MMU.load_uint64(RS1);
 MMU.store_uint64(RS1, std::max(RS2,v));
diff --git a/riscv/insns/amomaxu_w.h b/riscv/insns/amomaxu_w.h
index 448814b..fc83dc3 100644
--- a/riscv/insns/amomaxu_w.h
+++ b/riscv/insns/amomaxu_w.h
@@ -1,3 +1,4 @@
+require_extension('A');
 uint32_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, std::max(uint32_t(RS2),v));
 WRITE_RD((int32_t)v);
diff --git a/riscv/insns/amomin_d.h b/riscv/insns/amomin_d.h
index 2ad8eef..8d08984 100644
--- a/riscv/insns/amomin_d.h
+++ b/riscv/insns/amomin_d.h
@@ -1,3 +1,4 @@
+require_extension('A');
 require_rv64;
 sreg_t v = MMU.load_int64(RS1);
 MMU.store_uint64(RS1, std::min(sreg_t(RS2),v));
diff --git a/riscv/insns/amomin_w.h b/riscv/insns/amomin_w.h
index 28efa15..31a8df8 100644
--- a/riscv/insns/amomin_w.h
+++ b/riscv/insns/amomin_w.h
@@ -1,3 +1,4 @@
+require_extension('A');
 int32_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, std::min(int32_t(RS2),v));
 WRITE_RD(v);
diff --git a/riscv/insns/amominu_d.h b/riscv/insns/amominu_d.h
index 88fe724..8a77edc 100644
--- a/riscv/insns/amominu_d.h
+++ b/riscv/insns/amominu_d.h
@@ -1,3 +1,4 @@
+require_extension('A');
 require_rv64;
 reg_t v = MMU.load_uint64(RS1);
 MMU.store_uint64(RS1, std::min(RS2,v));
diff --git a/riscv/insns/amominu_w.h b/riscv/insns/amominu_w.h
index 459b201..2b6aaa3 100644
--- a/riscv/insns/amominu_w.h
+++ b/riscv/insns/amominu_w.h
@@ -1,3 +1,4 @@
+require_extension('A');
 uint32_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, std::min(uint32_t(RS2),v));
 WRITE_RD((int32_t)v);
diff --git a/riscv/insns/amoor_d.h b/riscv/insns/amoor_d.h
index 58a64e0..5a69717 100644
--- a/riscv/insns/amoor_d.h
+++ b/riscv/insns/amoor_d.h
@@ -1,3 +1,4 @@
+require_extension('A');
 require_rv64;
 reg_t v = MMU.load_uint64(RS1);
 MMU.store_uint64(RS1, RS2 | v);
diff --git a/riscv/insns/amoor_w.h b/riscv/insns/amoor_w.h
index c178f9a..f5b96b9 100644
--- a/riscv/insns/amoor_w.h
+++ b/riscv/insns/amoor_w.h
@@ -1,3 +1,4 @@
+require_extension('A');
 reg_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, RS2 | v);
 WRITE_RD(v);
diff --git a/riscv/insns/amoswap_d.h b/riscv/insns/amoswap_d.h
index 9f34eaa..8cf1411 100644
--- a/riscv/insns/amoswap_d.h
+++ b/riscv/insns/amoswap_d.h
@@ -1,3 +1,4 @@
+require_extension('A');
 require_rv64;
 reg_t v = MMU.load_uint64(RS1);
 MMU.store_uint64(RS1, RS2);
diff --git a/riscv/insns/amoswap_w.h b/riscv/insns/amoswap_w.h
index 148b5bc..0764d59 100644
--- a/riscv/insns/amoswap_w.h
+++ b/riscv/insns/amoswap_w.h
@@ -1,3 +1,4 @@
+require_extension('A');
 reg_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, RS2);
 WRITE_RD(v);
diff --git a/riscv/insns/amoxor_d.h b/riscv/insns/amoxor_d.h
index acd8b61..3970822 100644
--- a/riscv/insns/amoxor_d.h
+++ b/riscv/insns/amoxor_d.h
@@ -1,3 +1,4 @@
+require_extension('A');
 require_rv64;
 reg_t v = MMU.load_uint64(RS1);
 MMU.store_uint64(RS1, RS2 ^ v);
diff --git a/riscv/insns/amoxor_w.h b/riscv/insns/amoxor_w.h
index 3a87b6e..9889b64 100644
--- a/riscv/insns/amoxor_w.h
+++ b/riscv/insns/amoxor_w.h
@@ -1,3 +1,4 @@
+require_extension('A');
 reg_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, RS2 ^ v);
 WRITE_RD(v);
diff --git a/riscv/insns/c_add.h b/riscv/insns/c_add.h
index b2ba34f..c349fc0 100644
--- a/riscv/insns/c_add.h
+++ b/riscv/insns/c_add.h
@@ -1,2 +1,2 @@
-require_rvc;
+require_extension('C');
 WRITE_RD(sext_xlen(RVC_RS1 + RVC_RS2));
diff --git a/riscv/insns/c_addi.h b/riscv/insns/c_addi.h
index 762f5c2..ad278f1 100644
--- a/riscv/insns/c_addi.h
+++ b/riscv/insns/c_addi.h
@@ -1,2 +1,2 @@
-require_rvc;
+require_extension('C');
 WRITE_RD(sext_xlen(RVC_RS2 + insn.rvc_imm()));
diff --git a/riscv/insns/c_addi4.h b/riscv/insns/c_addi4.h
index 90f3d81..3c9b7b2 100644
--- a/riscv/insns/c_addi4.h
+++ b/riscv/insns/c_addi4.h
@@ -1,2 +1,2 @@
-require_rvc;
+require_extension('C');
 WRITE_RD(sext_xlen(RVC_RS2 + insn.rvc_lwsp_imm()));
diff --git a/riscv/insns/c_addiw.h b/riscv/insns/c_addiw.h
index 33f970c..1b81834 100644
--- a/riscv/insns/c_addiw.h
+++ b/riscv/insns/c_addiw.h
@@ -1,3 +1,3 @@
-require_rvc;
+require_extension('C');
 require_rv64;
 WRITE_RD(sext32(RVC_RS2 + insn.rvc_imm()));
diff --git a/riscv/insns/c_addw.h b/riscv/insns/c_addw.h
index c474cda..fef554d 100644
--- a/riscv/insns/c_addw.h
+++ b/riscv/insns/c_addw.h
@@ -1,3 +1,3 @@
-require_rvc;
+require_extension('C');
 require_rv64;
 WRITE_RD(sext32(RVC_RS1 + RVC_RS2));
diff --git a/riscv/insns/c_beqz.h b/riscv/insns/c_beqz.h
index 8fee5bc..35c1196 100644
--- a/riscv/insns/c_beqz.h
+++ b/riscv/insns/c_beqz.h
@@ -1,3 +1,3 @@
-require_rvc;
+require_extension('C');
 if (RVC_RS1S == 0)
   set_pc(pc + insn.rvc_b_imm());
diff --git a/riscv/insns/c_bnez.h b/riscv/insns/c_bnez.h
index a1a5666..1e40ea7 100644
--- a/riscv/insns/c_bnez.h
+++ b/riscv/insns/c_bnez.h
@@ -1,3 +1,3 @@
-require_rvc;
+require_extension('C');
 if (RVC_RS1S != 0)
   set_pc(pc + insn.rvc_b_imm());
diff --git a/riscv/insns/c_j.h b/riscv/insns/c_j.h
index f57022d..6d8939c 100644
--- a/riscv/insns/c_j.h
+++ b/riscv/insns/c_j.h
@@ -1,2 +1,2 @@
-require_rvc;
+require_extension('C');
 set_pc(pc + insn.rvc_j_imm());
diff --git a/riscv/insns/c_jalr.h b/riscv/insns/c_jalr.h
index 9fd7f5d..ef6edfc 100644
--- a/riscv/insns/c_jalr.h
+++ b/riscv/insns/c_jalr.h
@@ -1,4 +1,4 @@
-require_rvc;
+require_extension('C');
 reg_t tmp = npc;
 set_pc(RVC_RS1 & ~reg_t(1));
 WRITE_RD(tmp);
diff --git a/riscv/insns/c_ld.h b/riscv/insns/c_ld.h
index 37b0ee2..df0f5c3 100644
--- a/riscv/insns/c_ld.h
+++ b/riscv/insns/c_ld.h
@@ -1,3 +1,3 @@
-require_rvc;
+require_extension('C');
 require_rv64;
 WRITE_RVC_RDS(MMU.load_int64(RVC_RS1S + insn.rvc_ld_imm()));
diff --git a/riscv/insns/c_ldsp.h b/riscv/insns/c_ldsp.h
index 0b8bcbe..42665cf 100644
--- a/riscv/insns/c_ldsp.h
+++ b/riscv/insns/c_ldsp.h
@@ -1,3 +1,3 @@
-require_rvc;
+require_extension('C');
 require_rv64;
 WRITE_RD(MMU.load_int64(RVC_SP + insn.rvc_ldsp_imm()));
diff --git a/riscv/insns/c_li.h b/riscv/insns/c_li.h
index b53c958..06d7bf2 100644
--- a/riscv/insns/c_li.h
+++ b/riscv/insns/c_li.h
@@ -1,4 +1,4 @@
-require_rvc;
+require_extension('C');
 if (insn.rvc_rd() == 0) {
   if (insn.rvc_imm() == -32) // c.sbreak
     throw trap_breakpoint();
diff --git a/riscv/insns/c_lui.h b/riscv/insns/c_lui.h
index abdb78e..4bd4f87 100644
--- a/riscv/insns/c_lui.h
+++ b/riscv/insns/c_lui.h
@@ -1,2 +1,2 @@
-require_rvc;
+require_extension('C');
 WRITE_RD(insn.rvc_imm() << 12);
diff --git a/riscv/insns/c_lw.h b/riscv/insns/c_lw.h
index 9c6f470..f2fc299 100644
--- a/riscv/insns/c_lw.h
+++ b/riscv/insns/c_lw.h
@@ -1,2 +1,2 @@
-require_rvc;
+require_extension('C');
 WRITE_RVC_RDS(MMU.load_int32(RVC_RS1S + insn.rvc_lw_imm()));
diff --git a/riscv/insns/c_lwsp.h b/riscv/insns/c_lwsp.h
index 8d9b9e3..ed4dcf3 100644
--- a/riscv/insns/c_lwsp.h
+++ b/riscv/insns/c_lwsp.h
@@ -1,2 +1,2 @@
-require_rvc;
+require_extension('C');
 WRITE_RD(MMU.load_int32(RVC_SP + insn.rvc_lwsp_imm()));
diff --git a/riscv/insns/c_mv.h b/riscv/insns/c_mv.h
index 6de6584..bc05cfe 100644
--- a/riscv/insns/c_mv.h
+++ b/riscv/insns/c_mv.h
@@ -1,2 +1,2 @@
-require_rvc;
+require_extension('C');
 WRITE_RD(RVC_RS1);
diff --git a/riscv/insns/c_sd.h b/riscv/insns/c_sd.h
index 13de934..9262d04 100644
--- a/riscv/insns/c_sd.h
+++ b/riscv/insns/c_sd.h
@@ -1,3 +1,3 @@
-require_rvc;
+require_extension('C');
 require_rv64;
 MMU.store_uint64(RVC_RS1S + insn.rvc_ld_imm(), RVC_RS2S);
diff --git a/riscv/insns/c_sdsp.h b/riscv/insns/c_sdsp.h
index 6028b0f..e8b5170 100644
--- a/riscv/insns/c_sdsp.h
+++ b/riscv/insns/c_sdsp.h
@@ -1,3 +1,3 @@
-require_rvc;
+require_extension('C');
 require_rv64;
 MMU.store_uint64(RVC_SP + insn.rvc_ldsp_imm(), RVC_RS2);
diff --git a/riscv/insns/c_slli.h b/riscv/insns/c_slli.h
index fb6dffd..de3683b 100644
--- a/riscv/insns/c_slli.h
+++ b/riscv/insns/c_slli.h
@@ -1,4 +1,4 @@
-require_rvc;
+require_extension('C');
 if (insn.rvc_imm() >= xlen)
   throw trap_illegal_instruction();
 WRITE_RD(sext_xlen(RVC_RS2 << insn.rvc_imm()));
diff --git a/riscv/insns/c_sw.h b/riscv/insns/c_sw.h
index 34deb9d..3073e9d 100644
--- a/riscv/insns/c_sw.h
+++ b/riscv/insns/c_sw.h
@@ -1,2 +1,2 @@
-require_rvc;
+require_extension('C');
 MMU.store_uint32(RVC_RS1S + insn.rvc_lw_imm(), RVC_RS2S);
diff --git a/riscv/insns/c_swsp.h b/riscv/insns/c_swsp.h
index bbb5ad0..6f3fef0 100644
--- a/riscv/insns/c_swsp.h
+++ b/riscv/insns/c_swsp.h
@@ -1,2 +1,2 @@
-require_rvc;
+require_extension('C');
 MMU.store_uint32(RVC_SP + insn.rvc_lwsp_imm(), RVC_RS2);
diff --git a/riscv/insns/div.h b/riscv/insns/div.h
index 3ad613a..9cbe8d6 100644
--- a/riscv/insns/div.h
+++ b/riscv/insns/div.h
@@ -1,3 +1,4 @@
+require_extension('M');
 sreg_t lhs = sext_xlen(RS1);
 sreg_t rhs = sext_xlen(RS2);
 if(rhs == 0)
diff --git a/riscv/insns/divu.h b/riscv/insns/divu.h
index 4887ce0..31d7585 100644
--- a/riscv/insns/divu.h
+++ b/riscv/insns/divu.h
@@ -1,3 +1,4 @@
+require_extension('M');
 reg_t lhs = zext_xlen(RS1);
 reg_t rhs = zext_xlen(RS2);
 if(rhs == 0)
diff --git a/riscv/insns/divuw.h b/riscv/insns/divuw.h
index a613d95..e127619 100644
--- a/riscv/insns/divuw.h
+++ b/riscv/insns/divuw.h
@@ -1,3 +1,4 @@
+require_extension('M');
 require_rv64;
 reg_t lhs = zext32(RS1);
 reg_t rhs = zext32(RS2);
diff --git a/riscv/insns/divw.h b/riscv/insns/divw.h
index bd4e999..11be17e 100644
--- a/riscv/insns/divw.h
+++ b/riscv/insns/divw.h
@@ -1,3 +1,4 @@
+require_extension('M');
 require_rv64;
 sreg_t lhs = sext32(RS1);
 sreg_t rhs = sext32(RS2);
diff --git a/riscv/insns/fadd_d.h b/riscv/insns/fadd_d.h
index e06efb8..3e5963d 100644
--- a/riscv/insns/fadd_d.h
+++ b/riscv/insns/fadd_d.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(f64_mulAdd(FRS1, 0x3ff0000000000000ULL, FRS2));
diff --git a/riscv/insns/fadd_h.h b/riscv/insns/fadd_h.h
deleted file mode 100644
index e69de29..0000000
--- a/riscv/insns/fadd_h.h
+++ /dev/null
diff --git a/riscv/insns/fadd_s.h b/riscv/insns/fadd_s.h
index c43135d..a35a524 100644
--- a/riscv/insns/fadd_s.h
+++ b/riscv/insns/fadd_s.h
@@ -1,3 +1,4 @@
+require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(f32_mulAdd(FRS1, 0x3f800000, FRS2));
diff --git a/riscv/insns/fclass_d.h b/riscv/insns/fclass_d.h
index bd42d45..f4883ef 100644
--- a/riscv/insns/fclass_d.h
+++ b/riscv/insns/fclass_d.h
@@ -1,2 +1,3 @@
+require_extension('D');
 require_fp;
 WRITE_RD(f64_classify(FRS1));
diff --git a/riscv/insns/fclass_s.h b/riscv/insns/fclass_s.h
index a010266..a2d5b63 100644
--- a/riscv/insns/fclass_s.h
+++ b/riscv/insns/fclass_s.h
@@ -1,2 +1,3 @@
+require_extension('F');
 require_fp;
 WRITE_RD(f32_classify(FRS1));
diff --git a/riscv/insns/fcvt_d_h.h b/riscv/insns/fcvt_d_h.h
deleted file mode 100644
index e69de29..0000000
--- a/riscv/insns/fcvt_d_h.h
+++ /dev/null
diff --git a/riscv/insns/fcvt_d_l.h b/riscv/insns/fcvt_d_l.h
index e0e1824..08716cf 100644
--- a/riscv/insns/fcvt_d_l.h
+++ b/riscv/insns/fcvt_d_l.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
diff --git a/riscv/insns/fcvt_d_lu.h b/riscv/insns/fcvt_d_lu.h
index ee33848..306d7fe 100644
--- a/riscv/insns/fcvt_d_lu.h
+++ b/riscv/insns/fcvt_d_lu.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
diff --git a/riscv/insns/fcvt_d_s.h b/riscv/insns/fcvt_d_s.h
index 0024330..177e77c 100644
--- a/riscv/insns/fcvt_d_s.h
+++ b/riscv/insns/fcvt_d_s.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(f32_to_f64(FRS1));
diff --git a/riscv/insns/fcvt_d_w.h b/riscv/insns/fcvt_d_w.h
index ce56974..4c4861c 100644
--- a/riscv/insns/fcvt_d_w.h
+++ b/riscv/insns/fcvt_d_w.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(i32_to_f64((int32_t)RS1));
diff --git a/riscv/insns/fcvt_d_wu.h b/riscv/insns/fcvt_d_wu.h
index 4c56248..1dbf218 100644
--- a/riscv/insns/fcvt_d_wu.h
+++ b/riscv/insns/fcvt_d_wu.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(ui32_to_f64((uint32_t)RS1));
diff --git a/riscv/insns/fcvt_h_d.h b/riscv/insns/fcvt_h_d.h
deleted file mode 100644
index e69de29..0000000
--- a/riscv/insns/fcvt_h_d.h
+++ /dev/null
diff --git a/riscv/insns/fcvt_h_l.h b/riscv/insns/fcvt_h_l.h
deleted file mode 100644
index e69de29..0000000
--- a/riscv/insns/fcvt_h_l.h
+++ /dev/null
diff --git a/riscv/insns/fcvt_h_lu.h b/riscv/insns/fcvt_h_lu.h
deleted file mode 100644
index e69de29..0000000
--- a/riscv/insns/fcvt_h_lu.h
+++ /dev/null
diff --git a/riscv/insns/fcvt_h_s.h b/riscv/insns/fcvt_h_s.h
deleted file mode 100644
index e69de29..0000000
--- a/riscv/insns/fcvt_h_s.h
+++ /dev/null
diff --git a/riscv/insns/fcvt_h_w.h b/riscv/insns/fcvt_h_w.h
deleted file mode 100644
index e69de29..0000000
--- a/riscv/insns/fcvt_h_w.h
+++ /dev/null
diff --git a/riscv/insns/fcvt_h_wu.h b/riscv/insns/fcvt_h_wu.h
deleted file mode 100644
index e69de29..0000000
--- a/riscv/insns/fcvt_h_wu.h
+++ /dev/null
diff --git a/riscv/insns/fcvt_l_d.h b/riscv/insns/fcvt_l_d.h
index 55dbe27..ee323f3 100644
--- a/riscv/insns/fcvt_l_d.h
+++ b/riscv/insns/fcvt_l_d.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
diff --git a/riscv/insns/fcvt_l_h.h b/riscv/insns/fcvt_l_h.h
deleted file mode 100644
index e69de29..0000000
--- a/riscv/insns/fcvt_l_h.h
+++ /dev/null
diff --git a/riscv/insns/fcvt_l_s.h b/riscv/insns/fcvt_l_s.h
index ea1e5a7..6079a69 100644
--- a/riscv/insns/fcvt_l_s.h
+++ b/riscv/insns/fcvt_l_s.h
@@ -1,3 +1,4 @@
+require_extension('F');
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
diff --git a/riscv/insns/fcvt_lu_d.h b/riscv/insns/fcvt_lu_d.h
index 7be12ed..b6004ea 100644
--- a/riscv/insns/fcvt_lu_d.h
+++ b/riscv/insns/fcvt_lu_d.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
diff --git a/riscv/insns/fcvt_lu_h.h b/riscv/insns/fcvt_lu_h.h
deleted file mode 100644
index e69de29..0000000
--- a/riscv/insns/fcvt_lu_h.h
+++ /dev/null
diff --git a/riscv/insns/fcvt_lu_s.h b/riscv/insns/fcvt_lu_s.h
index 04501c1..af8e1ab 100644
--- a/riscv/insns/fcvt_lu_s.h
+++ b/riscv/insns/fcvt_lu_s.h
@@ -1,3 +1,4 @@
+require_extension('F');
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
diff --git a/riscv/insns/fcvt_s_d.h b/riscv/insns/fcvt_s_d.h
index 28a1d69..c1c9f0c 100644
--- a/riscv/insns/fcvt_s_d.h
+++ b/riscv/insns/fcvt_s_d.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(f64_to_f32(FRS1));
diff --git a/riscv/insns/fcvt_s_h.h b/riscv/insns/fcvt_s_h.h
deleted file mode 100644
index e69de29..0000000
--- a/riscv/insns/fcvt_s_h.h
+++ /dev/null
diff --git a/riscv/insns/fcvt_s_l.h b/riscv/insns/fcvt_s_l.h
index 723b9e4..9abcc80 100644
--- a/riscv/insns/fcvt_s_l.h
+++ b/riscv/insns/fcvt_s_l.h
@@ -1,3 +1,4 @@
+require_extension('F');
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
diff --git a/riscv/insns/fcvt_s_lu.h b/riscv/insns/fcvt_s_lu.h
index b58b395..70c676e 100644
--- a/riscv/insns/fcvt_s_lu.h
+++ b/riscv/insns/fcvt_s_lu.h
@@ -1,3 +1,4 @@
+require_extension('F');
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
diff --git a/riscv/insns/fcvt_s_w.h b/riscv/insns/fcvt_s_w.h
index 05445fa..1ddabd8 100644
--- a/riscv/insns/fcvt_s_w.h
+++ b/riscv/insns/fcvt_s_w.h
@@ -1,3 +1,4 @@
+require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(i32_to_f32((int32_t)RS1));
diff --git a/riscv/insns/fcvt_s_wu.h b/riscv/insns/fcvt_s_wu.h
index ca8d2b6..c1394c3 100644
--- a/riscv/insns/fcvt_s_wu.h
+++ b/riscv/insns/fcvt_s_wu.h
@@ -1,3 +1,4 @@
+require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(ui32_to_f32((uint32_t)RS1));
diff --git a/riscv/insns/fcvt_w_d.h b/riscv/insns/fcvt_w_d.h
index a5186b5..bac8a9b 100644
--- a/riscv/insns/fcvt_w_d.h
+++ b/riscv/insns/fcvt_w_d.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_RD(sext32(f64_to_i32(FRS1, RM, true)));
diff --git a/riscv/insns/fcvt_w_h.h b/riscv/insns/fcvt_w_h.h
deleted file mode 100644
index e69de29..0000000
--- a/riscv/insns/fcvt_w_h.h
+++ /dev/null
diff --git a/riscv/insns/fcvt_w_s.h b/riscv/insns/fcvt_w_s.h
index 1d82deb..81bc89f 100644
--- a/riscv/insns/fcvt_w_s.h
+++ b/riscv/insns/fcvt_w_s.h
@@ -1,3 +1,4 @@
+require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_RD(sext32(f32_to_i32(FRS1, RM, true)));
diff --git a/riscv/insns/fcvt_wu_d.h b/riscv/insns/fcvt_wu_d.h
index 5cf44d1..353ae6d 100644
--- a/riscv/insns/fcvt_wu_d.h
+++ b/riscv/insns/fcvt_wu_d.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_RD(sext32(f64_to_ui32(FRS1, RM, true)));
diff --git a/riscv/insns/fcvt_wu_h.h b/riscv/insns/fcvt_wu_h.h
deleted file mode 100644
index e69de29..0000000
--- a/riscv/insns/fcvt_wu_h.h
+++ /dev/null
diff --git a/riscv/insns/fcvt_wu_s.h b/riscv/insns/fcvt_wu_s.h
index 5b4c444..2c1ff00 100644
--- a/riscv/insns/fcvt_wu_s.h
+++ b/riscv/insns/fcvt_wu_s.h
@@ -1,3 +1,4 @@
+require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_RD(sext32(f32_to_ui32(FRS1, RM, true)));
diff --git a/riscv/insns/fdiv_d.h b/riscv/insns/fdiv_d.h
index e215702..d52ac66 100644
--- a/riscv/insns/fdiv_d.h
+++ b/riscv/insns/fdiv_d.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(f64_div(FRS1, FRS2));
diff --git a/riscv/insns/fdiv_h.h b/riscv/insns/fdiv_h.h
deleted file mode 100644
index e69de29..0000000
--- a/riscv/insns/fdiv_h.h
+++ /dev/null
diff --git a/riscv/insns/fdiv_s.h b/riscv/insns/fdiv_s.h
index 2644d08..cf54c57 100644
--- a/riscv/insns/fdiv_s.h
+++ b/riscv/insns/fdiv_s.h
@@ -1,3 +1,4 @@
+require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(f32_div(FRS1, FRS2));
diff --git a/riscv/insns/feq_d.h b/riscv/insns/feq_d.h
index 516fb59..43d9c1c 100644
--- a/riscv/insns/feq_d.h
+++ b/riscv/insns/feq_d.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 WRITE_RD(f64_eq(FRS1, FRS2));
 set_fp_exceptions;
diff --git a/riscv/insns/feq_h.h b/riscv/insns/feq_h.h
deleted file mode 100644
index e69de29..0000000
--- a/riscv/insns/feq_h.h
+++ /dev/null
diff --git a/riscv/insns/feq_s.h b/riscv/insns/feq_s.h
index b44da24..7d42634 100644
--- a/riscv/insns/feq_s.h
+++ b/riscv/insns/feq_s.h
@@ -1,3 +1,4 @@
+require_extension('F');
 require_fp;
 WRITE_RD(f32_eq(FRS1, FRS2));
 set_fp_exceptions;
diff --git a/riscv/insns/fld.h b/riscv/insns/fld.h
index 1bc83cf..0b50b8a 100644
--- a/riscv/insns/fld.h
+++ b/riscv/insns/fld.h
@@ -1,2 +1,3 @@
+require_extension('D');
 require_fp;
 WRITE_FRD(MMU.load_int64(RS1 + insn.i_imm()));
diff --git a/riscv/insns/fle_d.h b/riscv/insns/fle_d.h
index 72dcc7e..7f6a84d 100644
--- a/riscv/insns/fle_d.h
+++ b/riscv/insns/fle_d.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 WRITE_RD(f64_le(FRS1, FRS2));
 set_fp_exceptions;
diff --git a/riscv/insns/fle_h.h b/riscv/insns/fle_h.h
deleted file mode 100644
index e69de29..0000000
--- a/riscv/insns/fle_h.h
+++ /dev/null
diff --git a/riscv/insns/fle_s.h b/riscv/insns/fle_s.h
index 9c85b4a..0884c51 100644
--- a/riscv/insns/fle_s.h
+++ b/riscv/insns/fle_s.h
@@ -1,3 +1,4 @@
+require_extension('F');
 require_fp;
 WRITE_RD(f32_le(FRS1, FRS2));
 set_fp_exceptions;
diff --git a/riscv/insns/flh.h b/riscv/insns/flh.h
deleted file mode 100644
index e69de29..0000000
--- a/riscv/insns/flh.h
+++ /dev/null
diff --git a/riscv/insns/flt_d.h b/riscv/insns/flt_d.h
index 335e4a8..9fda98d 100644
--- a/riscv/insns/flt_d.h
+++ b/riscv/insns/flt_d.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 WRITE_RD(f64_lt(FRS1, FRS2));
 set_fp_exceptions;
diff --git a/riscv/insns/flt_h.h b/riscv/insns/flt_h.h
deleted file mode 100644
index e69de29..0000000
--- a/riscv/insns/flt_h.h
+++ /dev/null
diff --git a/riscv/insns/flt_s.h b/riscv/insns/flt_s.h
index 7a21785..830b0a0 100644
--- a/riscv/insns/flt_s.h
+++ b/riscv/insns/flt_s.h
@@ -1,3 +1,4 @@
+require_extension('F');
 require_fp;
 WRITE_RD(f32_lt(FRS1, FRS2));
 set_fp_exceptions;
diff --git a/riscv/insns/flw.h b/riscv/insns/flw.h
index a5f7d16..b94ba5d 100644
--- a/riscv/insns/flw.h
+++ b/riscv/insns/flw.h
@@ -1,2 +1,3 @@
+require_extension('F');
 require_fp;
 WRITE_FRD(MMU.load_int32(RS1 + insn.i_imm()));
diff --git a/riscv/insns/fmadd_d.h b/riscv/insns/fmadd_d.h
index 8640e7f..8605e0b 100644
--- a/riscv/insns/fmadd_d.h
+++ b/riscv/insns/fmadd_d.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(f64_mulAdd(FRS1, FRS2, FRS3));
diff --git a/riscv/insns/fmadd_h.h b/riscv/insns/fmadd_h.h
deleted file mode 100644
index e69de29..0000000
--- a/riscv/insns/fmadd_h.h
+++ /dev/null
diff --git a/riscv/insns/fmadd_s.h b/riscv/insns/fmadd_s.h
index f8b0a5f..95196b7 100644
--- a/riscv/insns/fmadd_s.h
+++ b/riscv/insns/fmadd_s.h
@@ -1,3 +1,4 @@
+require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(f32_mulAdd(FRS1, FRS2, FRS3));
diff --git a/riscv/insns/fmax_d.h b/riscv/insns/fmax_d.h
index a26aeab..eb156de 100644
--- a/riscv/insns/fmax_d.h
+++ b/riscv/insns/fmax_d.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 WRITE_FRD(isNaNF64UI(FRS2) || f64_le_quiet(FRS2,FRS1) /* && FRS1 not NaN */
       ? FRS1 : FRS2);
diff --git a/riscv/insns/fmax_h.h b/riscv/insns/fmax_h.h
deleted file mode 100644
index e69de29..0000000
--- a/riscv/insns/fmax_h.h
+++ /dev/null
diff --git a/riscv/insns/fmax_s.h b/riscv/insns/fmax_s.h
index b16134b..215a6d1 100644
--- a/riscv/insns/fmax_s.h
+++ b/riscv/insns/fmax_s.h
@@ -1,3 +1,4 @@
+require_extension('F');
 require_fp;
 WRITE_FRD(isNaNF32UI(FRS2) || f32_le_quiet(FRS2,FRS1) /* && FRS1 not NaN */
       ? FRS1 : FRS2);
diff --git a/riscv/insns/fmin_d.h b/riscv/insns/fmin_d.h
index c095ade..02ea681 100644
--- a/riscv/insns/fmin_d.h
+++ b/riscv/insns/fmin_d.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 WRITE_FRD(isNaNF64UI(FRS2) || f64_lt_quiet(FRS1,FRS2) /* && FRS1 not NaN */
       ? FRS1 : FRS2);
diff --git a/riscv/insns/fmin_h.h b/riscv/insns/fmin_h.h
deleted file mode 100644
index e69de29..0000000
--- a/riscv/insns/fmin_h.h
+++ /dev/null
diff --git a/riscv/insns/fmin_s.h b/riscv/insns/fmin_s.h
index e2fdc5c..cc673a0 100644
--- a/riscv/insns/fmin_s.h
+++ b/riscv/insns/fmin_s.h
@@ -1,3 +1,4 @@
+require_extension('F');
 require_fp;
 WRITE_FRD(isNaNF32UI(FRS2) || f32_lt_quiet(FRS1,FRS2) /* && FRS1 not NaN */
       ? FRS1 : FRS2);
diff --git a/riscv/insns/fmsub_d.h b/riscv/insns/fmsub_d.h
index 13e9fcc..696f822 100644
--- a/riscv/insns/fmsub_d.h
+++ b/riscv/insns/fmsub_d.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(f64_mulAdd(FRS1, FRS2, FRS3 ^ (uint64_t)INT64_MIN));
diff --git a/riscv/insns/fmsub_h.h b/riscv/insns/fmsub_h.h
deleted file mode 100644
index e69de29..0000000
--- a/riscv/insns/fmsub_h.h
+++ /dev/null
diff --git a/riscv/insns/fmsub_s.h b/riscv/insns/fmsub_s.h
index c6aa418..9251277 100644
--- a/riscv/insns/fmsub_s.h
+++ b/riscv/insns/fmsub_s.h
@@ -1,3 +1,4 @@
+require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(f32_mulAdd(FRS1, FRS2, FRS3 ^ (uint32_t)INT32_MIN));
diff --git a/riscv/insns/fmul_d.h b/riscv/insns/fmul_d.h
index e2ca1c2..d74c316 100644
--- a/riscv/insns/fmul_d.h
+++ b/riscv/insns/fmul_d.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(f64_mulAdd(FRS1, FRS2, (FRS1 ^ FRS2) & (uint64_t)INT64_MIN));
diff --git a/riscv/insns/fmul_h.h b/riscv/insns/fmul_h.h
deleted file mode 100644
index e69de29..0000000
--- a/riscv/insns/fmul_h.h
+++ /dev/null
diff --git a/riscv/insns/fmul_s.h b/riscv/insns/fmul_s.h
index f564803..284aeb3 100644
--- a/riscv/insns/fmul_s.h
+++ b/riscv/insns/fmul_s.h
@@ -1,3 +1,4 @@
+require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(f32_mulAdd(FRS1, FRS2, (FRS1 ^ FRS2) & (uint32_t)INT32_MIN));
diff --git a/riscv/insns/fmv_d_x.h b/riscv/insns/fmv_d_x.h
index f01811d..c3f6049 100644
--- a/riscv/insns/fmv_d_x.h
+++ b/riscv/insns/fmv_d_x.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_rv64;
 require_fp;
 WRITE_FRD(RS1);
diff --git a/riscv/insns/fmv_h_x.h b/riscv/insns/fmv_h_x.h
deleted file mode 100644
index e69de29..0000000
--- a/riscv/insns/fmv_h_x.h
+++ /dev/null
diff --git a/riscv/insns/fmv_s_x.h b/riscv/insns/fmv_s_x.h
index f3eac82..f0f95ac 100644
--- a/riscv/insns/fmv_s_x.h
+++ b/riscv/insns/fmv_s_x.h
@@ -1,2 +1,3 @@
+require_extension('F');
 require_fp;
 WRITE_FRD(RS1);
diff --git a/riscv/insns/fmv_x_d.h b/riscv/insns/fmv_x_d.h
index d3c1d7a..b97d7f5 100644
--- a/riscv/insns/fmv_x_d.h
+++ b/riscv/insns/fmv_x_d.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_rv64;
 require_fp;
 WRITE_RD(FRS1);
diff --git a/riscv/insns/fmv_x_h.h b/riscv/insns/fmv_x_h.h
deleted file mode 100644
index e69de29..0000000
--- a/riscv/insns/fmv_x_h.h
+++ /dev/null
diff --git a/riscv/insns/fmv_x_s.h b/riscv/insns/fmv_x_s.h
index 46a9488..1bee87f 100644
--- a/riscv/insns/fmv_x_s.h
+++ b/riscv/insns/fmv_x_s.h
@@ -1,2 +1,3 @@
+require_extension('F');
 require_fp;
 WRITE_RD(sext32(FRS1));
diff --git a/riscv/insns/fnmadd_d.h b/riscv/insns/fnmadd_d.h
index 705470b..bed6172 100644
--- a/riscv/insns/fnmadd_d.h
+++ b/riscv/insns/fnmadd_d.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(f64_mulAdd(FRS1 ^ (uint64_t)INT64_MIN, FRS2, FRS3 ^ (uint64_t)INT64_MIN));
diff --git a/riscv/insns/fnmadd_h.h b/riscv/insns/fnmadd_h.h
deleted file mode 100644
index e69de29..0000000
--- a/riscv/insns/fnmadd_h.h
+++ /dev/null
diff --git a/riscv/insns/fnmadd_s.h b/riscv/insns/fnmadd_s.h
index 2df321b..1378ae3 100644
--- a/riscv/insns/fnmadd_s.h
+++ b/riscv/insns/fnmadd_s.h
@@ -1,3 +1,4 @@
+require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(f32_mulAdd(FRS1 ^ (uint32_t)INT32_MIN, FRS2, FRS3 ^ (uint32_t)INT32_MIN));
diff --git a/riscv/insns/fnmsub_d.h b/riscv/insns/fnmsub_d.h
index c38d2bf..340090a 100644
--- a/riscv/insns/fnmsub_d.h
+++ b/riscv/insns/fnmsub_d.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(f64_mulAdd(FRS1 ^ (uint64_t)INT64_MIN, FRS2, FRS3));
diff --git a/riscv/insns/fnmsub_h.h b/riscv/insns/fnmsub_h.h
deleted file mode 100644
index e69de29..0000000
--- a/riscv/insns/fnmsub_h.h
+++ /dev/null
diff --git a/riscv/insns/fnmsub_s.h b/riscv/insns/fnmsub_s.h
index c3fa995..3be27d0 100644
--- a/riscv/insns/fnmsub_s.h
+++ b/riscv/insns/fnmsub_s.h
@@ -1,3 +1,4 @@
+require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(f32_mulAdd(FRS1 ^ (uint32_t)INT32_MIN, FRS2, FRS3));
diff --git a/riscv/insns/fsd.h b/riscv/insns/fsd.h
index fe90a6b..63cc8e5 100644
--- a/riscv/insns/fsd.h
+++ b/riscv/insns/fsd.h
@@ -1,2 +1,3 @@
+require_extension('D');
 require_fp;
 MMU.store_uint64(RS1 + insn.s_imm(), FRS2);
diff --git a/riscv/insns/fsgnj_d.h b/riscv/insns/fsgnj_d.h
index 74ef3f6..52648a1 100644
--- a/riscv/insns/fsgnj_d.h
+++ b/riscv/insns/fsgnj_d.h
@@ -1,2 +1,3 @@
+require_extension('D');
 require_fp;
 WRITE_FRD((FRS1 &~ INT64_MIN) | (FRS2 & INT64_MIN));
diff --git a/riscv/insns/fsgnj_h.h b/riscv/insns/fsgnj_h.h
deleted file mode 100644
index e69de29..0000000
--- a/riscv/insns/fsgnj_h.h
+++ /dev/null
diff --git a/riscv/insns/fsgnj_s.h b/riscv/insns/fsgnj_s.h
index 4f852b4..4c91ff3 100644
--- a/riscv/insns/fsgnj_s.h
+++ b/riscv/insns/fsgnj_s.h
@@ -1,2 +1,3 @@
+require_extension('F');
 require_fp;
 WRITE_FRD((FRS1 &~ (uint32_t)INT32_MIN) | (FRS2 & (uint32_t)INT32_MIN));
diff --git a/riscv/insns/fsgnjn_d.h b/riscv/insns/fsgnjn_d.h
index e214f1d..cdec924 100644
--- a/riscv/insns/fsgnjn_d.h
+++ b/riscv/insns/fsgnjn_d.h
@@ -1,2 +1,3 @@
+require_extension('D');
 require_fp;
 WRITE_FRD((FRS1 &~ INT64_MIN) | ((~FRS2) & INT64_MIN));
diff --git a/riscv/insns/fsgnjn_h.h b/riscv/insns/fsgnjn_h.h
deleted file mode 100644
index e69de29..0000000
--- a/riscv/insns/fsgnjn_h.h
+++ /dev/null
diff --git a/riscv/insns/fsgnjn_s.h b/riscv/insns/fsgnjn_s.h
index b098150..f91a7b0 100644
--- a/riscv/insns/fsgnjn_s.h
+++ b/riscv/insns/fsgnjn_s.h
@@ -1,2 +1,3 @@
+require_extension('F');
 require_fp;
 WRITE_FRD((FRS1 &~ (uint32_t)INT32_MIN) | ((~FRS2) & (uint32_t)INT32_MIN));
diff --git a/riscv/insns/fsgnjx_d.h b/riscv/insns/fsgnjx_d.h
index 2bcef6f..b09d24c 100644
--- a/riscv/insns/fsgnjx_d.h
+++ b/riscv/insns/fsgnjx_d.h
@@ -1,2 +1,3 @@
+require_extension('D');
 require_fp;
 WRITE_FRD(FRS1 ^ (FRS2 & INT64_MIN));
diff --git a/riscv/insns/fsgnjx_h.h b/riscv/insns/fsgnjx_h.h
deleted file mode 100644
index e69de29..0000000
--- a/riscv/insns/fsgnjx_h.h
+++ /dev/null
diff --git a/riscv/insns/fsgnjx_s.h b/riscv/insns/fsgnjx_s.h
index 69b2d98..1fd2de6 100644
--- a/riscv/insns/fsgnjx_s.h
+++ b/riscv/insns/fsgnjx_s.h
@@ -1,2 +1,3 @@
+require_extension('F');
 require_fp;
 WRITE_FRD(FRS1 ^ (FRS2 & (uint32_t)INT32_MIN));
diff --git a/riscv/insns/fsh.h b/riscv/insns/fsh.h
deleted file mode 100644
index e69de29..0000000
--- a/riscv/insns/fsh.h
+++ /dev/null
diff --git a/riscv/insns/fsqrt_d.h b/riscv/insns/fsqrt_d.h
index 0ff5daa..812438c 100644
--- a/riscv/insns/fsqrt_d.h
+++ b/riscv/insns/fsqrt_d.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(f64_sqrt(FRS1));
diff --git a/riscv/insns/fsqrt_h.h b/riscv/insns/fsqrt_h.h
deleted file mode 100644
index e69de29..0000000
--- a/riscv/insns/fsqrt_h.h
+++ /dev/null
diff --git a/riscv/insns/fsqrt_s.h b/riscv/insns/fsqrt_s.h
index ea1f31a..d77acab 100644
--- a/riscv/insns/fsqrt_s.h
+++ b/riscv/insns/fsqrt_s.h
@@ -1,3 +1,4 @@
+require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(f32_sqrt(FRS1));
diff --git a/riscv/insns/fsub_d.h b/riscv/insns/fsub_d.h
index 238ee9e..6ffc6b3 100644
--- a/riscv/insns/fsub_d.h
+++ b/riscv/insns/fsub_d.h
@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(f64_mulAdd(FRS1, 0x3ff0000000000000ULL, FRS2 ^ (uint64_t)INT64_MIN));
diff --git a/riscv/insns/fsub_h.h b/riscv/insns/fsub_h.h
deleted file mode 100644
index e69de29..0000000
--- a/riscv/insns/fsub_h.h
+++ /dev/null
diff --git a/riscv/insns/fsub_s.h b/riscv/insns/fsub_s.h
index a30b4f9..6a0f853 100644
--- a/riscv/insns/fsub_s.h
+++ b/riscv/insns/fsub_s.h
@@ -1,3 +1,4 @@
+require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(f32_mulAdd(FRS1, 0x3f800000, FRS2 ^ (uint32_t)INT32_MIN));
diff --git a/riscv/insns/fsw.h b/riscv/insns/fsw.h
index 85c8091..3135e9b 100644
--- a/riscv/insns/fsw.h
+++ b/riscv/insns/fsw.h
@@ -1,2 +1,3 @@
+require_extension('F');
 require_fp;
 MMU.store_uint32(RS1 + insn.s_imm(), FRS2);
diff --git a/riscv/insns/lr_d.h b/riscv/insns/lr_d.h
index 94c4bf7..077590f 100644
--- a/riscv/insns/lr_d.h
+++ b/riscv/insns/lr_d.h
@@ -1,3 +1,4 @@
+require_extension('A');
 require_rv64;
 p->get_state()->load_reservation = RS1;
 WRITE_RD(MMU.load_int64(RS1));
diff --git a/riscv/insns/lr_w.h b/riscv/insns/lr_w.h
index 2b95419..767251f 100644
--- a/riscv/insns/lr_w.h
+++ b/riscv/insns/lr_w.h
@@ -1,2 +1,3 @@
+require_extension('A');
 p->get_state()->load_reservation = RS1;
 WRITE_RD(MMU.load_int32(RS1));
diff --git a/riscv/insns/mul.h b/riscv/insns/mul.h
index c6b5331..0102d36 100644
--- a/riscv/insns/mul.h
+++ b/riscv/insns/mul.h
@@ -1 +1,2 @@
+require_extension('M');
 WRITE_RD(sext_xlen(RS1 * RS2));
diff --git a/riscv/insns/mulh.h b/riscv/insns/mulh.h
index 567e213..051382a 100644
--- a/riscv/insns/mulh.h
+++ b/riscv/insns/mulh.h
@@ -1,3 +1,4 @@
+require_extension('M');
 if (xlen == 64)
   WRITE_RD(mulh(RS1, RS2));
 else
diff --git a/riscv/insns/mulhsu.h b/riscv/insns/mulhsu.h
index 5eeb89c..c53f90b 100644
--- a/riscv/insns/mulhsu.h
+++ b/riscv/insns/mulhsu.h
@@ -1,3 +1,4 @@
+require_extension('M');
 if (xlen == 64)
   WRITE_RD(mulhsu(RS1, RS2));
 else
diff --git a/riscv/insns/mulhu.h b/riscv/insns/mulhu.h
index ce6a21e..1ae3650 100644
--- a/riscv/insns/mulhu.h
+++ b/riscv/insns/mulhu.h
@@ -1,3 +1,4 @@
+require_extension('M');
 if (xlen == 64)
   WRITE_RD(mulhu(RS1, RS2));
 else
diff --git a/riscv/insns/mulw.h b/riscv/insns/mulw.h
index 184dd41..ed55545 100644
--- a/riscv/insns/mulw.h
+++ b/riscv/insns/mulw.h
@@ -1,2 +1,3 @@
+require_extension('M');
 require_rv64;
 WRITE_RD(sext32(RS1 * RS2));
diff --git a/riscv/insns/rem.h b/riscv/insns/rem.h
index d074f26..8587995 100644
--- a/riscv/insns/rem.h
+++ b/riscv/insns/rem.h
@@ -1,3 +1,4 @@
+require_extension('M');
 sreg_t lhs = sext_xlen(RS1);
 sreg_t rhs = sext_xlen(RS2);
 if(rhs == 0)
diff --git a/riscv/insns/remu.h b/riscv/insns/remu.h
index c291947..e74774c 100644
--- a/riscv/insns/remu.h
+++ b/riscv/insns/remu.h
@@ -1,3 +1,4 @@
+require_extension('M');
 reg_t lhs = zext_xlen(RS1);
 reg_t rhs = zext_xlen(RS2);
 if(rhs == 0)
diff --git a/riscv/insns/remuw.h b/riscv/insns/remuw.h
index e487516..b239c8f 100644
--- a/riscv/insns/remuw.h
+++ b/riscv/insns/remuw.h
@@ -1,3 +1,4 @@
+require_extension('M');
 require_rv64;
 reg_t lhs = zext32(RS1);
 reg_t rhs = zext32(RS2);
diff --git a/riscv/insns/remw.h b/riscv/insns/remw.h
index 2bae1a8..56221cc 100644
--- a/riscv/insns/remw.h
+++ b/riscv/insns/remw.h
@@ -1,3 +1,4 @@
+require_extension('M');
 require_rv64;
 sreg_t lhs = sext32(RS1);
 sreg_t rhs = sext32(RS2);
diff --git a/riscv/insns/sc_d.h b/riscv/insns/sc_d.h
index 2108079..01a45ce 100644
--- a/riscv/insns/sc_d.h
+++ b/riscv/insns/sc_d.h
@@ -1,3 +1,4 @@
+require_extension('A');
 require_rv64;
 if (RS1 == p->get_state()->load_reservation)
 {
diff --git a/riscv/insns/sc_w.h b/riscv/insns/sc_w.h
index 729973d..68ec577 100644
--- a/riscv/insns/sc_w.h
+++ b/riscv/insns/sc_w.h
@@ -1,3 +1,4 @@
+require_extension('A');
 if (RS1 == p->get_state()->load_reservation)
 {
   MMU.store_uint32(RS1, RS2);
diff --git a/riscv/insns/sltiu.h b/riscv/insns/sltiu.h
index c4478fd..f398457 100644
--- a/riscv/insns/sltiu.h
+++ b/riscv/insns/sltiu.h
@@ -1 +1 @@
-WRITE_RD(RS1 < insn.i_imm());
+WRITE_RD(RS1 < reg_t(insn.i_imm()));