rvv: add integer/fixed-point/mask/reduction/permutation instructions

based on v-spec 0.7.1, support
  sections: 12/13/15.1 ~ 15.2/16/17
  element size: 8/16/32/64
  support ediv: 1

Signed-off-by: Bruce Hoult <bruce@hoult.org>
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: Dave Wen <dave.wen@sifive.com>

1 files changed, 29 insertions, 0 deletions

diff --git a/riscv/insns/vssubu_vv.h b/riscv/insns/vssubu_vv.h
new file mode 100644
index 0000000..c5c74fe
--- /dev/null
+++ b/riscv/insns/vssubu_vv.h
@@ -0,0 +1,29 @@
+// vssubu.vv vd, vs2, vs1
+VI_LOOP_BASE
+bool sat = false;
+
+switch (sew) {
+case e8: {
+  VV_U_PARAMS(e8);
+  vd = sat_subu<uint8_t>(vs2, vs1, sat);
+  break;
+}
+case e16: {
+  VV_U_PARAMS(e16);
+  vd = sat_subu<uint16_t>(vs2, vs1, sat);
+  break;
+}
+case e32: {
+  VV_U_PARAMS(e32);
+  vd = sat_subu<uint32_t>(vs2, vs1, sat);
+  break;
+}
+default: {
+  VV_U_PARAMS(e64);
+  vd = sat_subu<uint64_t>(vs2, vs1, sat);
+  break;
+}
+}
+P.VU.vxsat |= sat;
+
+VI_LOOP_END