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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2021-02-22 09:01:30 -0800 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2021-02-24 18:40:55 -0800 |
| commit | 60428fcc44e0b2cf2932f3e0ce6a66d54755dab6 (patch) | |
| tree | f4e6f19ff9d9a6182f4211516580f392b487c457 /riscv/insns/vsse32_v.h | |
| parent | 487f1b7cd8fc74e94ac76f8912ce8f3e335ba940 (diff) | |
| download | spike-60428fcc44e0b2cf2932f3e0ce6a66d54755dab6.zip spike-60428fcc44e0b2cf2932f3e0ce6a66d54755dab6.tar.gz spike-60428fcc44e0b2cf2932f3e0ce6a66d54755dab6.tar.bz2 | |
rvv: add vse1/vle1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/insns/vsse32_v.h')
| -rw-r--r-- | riscv/insns/vsse32_v.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/insns/vsse32_v.h b/riscv/insns/vsse32_v.h index 73bd272..80276b2 100644 --- a/riscv/insns/vsse32_v.h +++ b/riscv/insns/vsse32_v.h @@ -1,2 +1,2 @@ // vsse32.v and vssseg[2-8]e32.v -VI_ST(i * RS2, fn, uint32); +VI_ST(i * RS2, fn, uint32, false); |