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| author | Dave.Wen <dave.wen@sifive.com> | 2019-04-03 20:01:14 -0700 |
|---|---|---|
| committer | Dave.Wen <dave.wen@sifive.com> | 2019-04-03 20:01:14 -0700 |
| commit | eee73392fd93b1b5ef9381cee6b511e4dce972e5 (patch) | |
| tree | c2508b4e0ac2a71a9db046a29442ed9477976055 /riscv/insns/vsra_vv.h | |
| parent | 392054db9a9d5ea2cb912c2fa011b36b2f5bd92c (diff) | |
| download | spike-eee73392fd93b1b5ef9381cee6b511e4dce972e5.zip spike-eee73392fd93b1b5ef9381cee6b511e4dce972e5.tar.gz spike-eee73392fd93b1b5ef9381cee6b511e4dce972e5.tar.bz2 | |
rvv: Fixed the following instructions. Based on the new macros
vadd_v[vxi]
vand_v[vx]
vor_vx
vxor_vx
vsll_v[vxi]
vsra_v[vxi]
vsrl_v[vxi]
Diffstat (limited to 'riscv/insns/vsra_vv.h')
| -rw-r--r-- | riscv/insns/vsra_vv.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/insns/vsra_vv.h b/riscv/insns/vsra_vv.h index cccdb58..eef7714 100644 --- a/riscv/insns/vsra_vv.h +++ b/riscv/insns/vsra_vv.h @@ -1,5 +1,5 @@ // vsra VI_VV_LOOP ({ - WRITE_RD(sext_xlen(sext_xlen(vs1) >> (vs2 & (xlen-1)))); + vd = vsext(vs2 >> (vs1 & (sew - 1)), sew); }) |