rvv: add integer/fixed-point/mask/reduction/permutation instructions

based on v-spec 0.7.1, support
  sections: 12/13/15.1 ~ 15.2/16/17
  element size: 8/16/32/64
  support ediv: 1

Signed-off-by: Bruce Hoult <bruce@hoult.org>
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: Dave Wen <dave.wen@sifive.com>

1 files changed, 34 insertions, 0 deletions

diff --git a/riscv/insns/vsmul_vx.h b/riscv/insns/vsmul_vx.h
new file mode 100644
index 0000000..ef3751b
--- /dev/null
+++ b/riscv/insns/vsmul_vx.h
@@ -0,0 +1,34 @@
+// vsmul
+VRM xrm = P.VU.get_vround_mode();
+uint128_t int_max = (1ul << (P.VU.vsew - 1)) - 1;
+uint128_t int_min = - (1 << (P.VU.vsew - 1));
+uint128_t sign_mask = ((1ul << (P.VU.vsew - 1)));
+
+VI_VX_ULOOP
+({
+  uint128_t rs1_sign;
+  uint128_t vs2_sign;
+  uint128_t result_sign;
+
+  rs1_sign = rs1 & sign_mask;
+  vs2_sign = vs2 & sign_mask;
+  bool overflow = rs1 == vs2 && rs1 == int_min;
+
+  uint128_t result = (uint128_t)rs1 * (uint128_t)vs2;
+  result &= ((uint128_t)1llu << ((sew * 2) - 2)) - 1;
+  result_sign = (rs1_sign ^ vs2_sign) & sign_mask;
+  // rounding
+  INT_ROUNDING(result, xrm, sew - 1);
+
+  // unsigned shifting
+  result = result >> (sew - 1);
+
+  // saturation
+  if (overflow) {
+    result = int_max;
+    P.VU.vxsat = 1;
+  } else {
+    result |= result_sign;
+  }
+  vd = result;
+})