diff options
author | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-10-23 01:36:33 -0700 |
---|---|---|
committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-11-11 19:02:35 -0800 |
commit | e289b996c6ef60693b394b57bb53034c38eff4e4 (patch) | |
tree | 9cd36f16b3d07c1849ac219c70e0eebac3cb99ed /riscv/insns/vslidedown_vx.h | |
parent | c655b1cf465f59912ddb5b0dbd6f83f1d5516406 (diff) | |
download | spike-e289b996c6ef60693b394b57bb53034c38eff4e4.zip spike-e289b996c6ef60693b394b57bb53034c38eff4e4.tar.gz spike-e289b996c6ef60693b394b57bb53034c38eff4e4.tar.bz2 |
rvv: add reg checking rule to vslide instructions
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/insns/vslidedown_vx.h')
-rw-r--r-- | riscv/insns/vslidedown_vx.h | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/riscv/insns/vslidedown_vx.h b/riscv/insns/vslidedown_vx.h index 251740c..9881e0e 100644 --- a/riscv/insns/vslidedown_vx.h +++ b/riscv/insns/vslidedown_vx.h @@ -1,11 +1,17 @@ //vslidedown.vx vd, vs2, rs1 +require((insn.rs2() & (P.VU.vlmul - 1)) == 0); +require((insn.rd() & (P.VU.vlmul - 1)) == 0); +if (P.VU.vlmul > 1 && insn.v_vm() == 0) + require(insn.rd() != 0); + +const reg_t sh = RS1; VI_LOOP_BASE -reg_t offset = RS1 == (reg_t)-1 ? ((RS1 & (P.VU.vlmax * 2 - 1)) + i) : RS1; -bool is_valid = offset < P.VU.vlmax; +reg_t offset = 0; +bool is_valid = (i + sh) < P.VU.vlmax; -if (!is_valid) { - offset = 0; +if (is_valid) { + offset = sh; } switch (sew) { |