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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-04-09 01:47:51 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-04-09 18:34:00 -0700 |
| commit | 1077d07572007d664fd8f46da4dd43db3f0254ff (patch) | |
| tree | b2b7f15e571d442668ac69360b541f059dea6e35 /riscv/insns/vslide1up_vx.h | |
| parent | 38b2a00e6cfe7657fc193eb01d60f03659fbb6c3 (diff) | |
| download | spike-1077d07572007d664fd8f46da4dd43db3f0254ff.zip spike-1077d07572007d664fd8f46da4dd43db3f0254ff.tar.gz spike-1077d07572007d664fd8f46da4dd43db3f0254ff.tar.bz2 | |
rvv: vslide[1]up now allows mask overlap when LMUL=1
See https://github.com/riscv/riscv-v-spec/pull/407
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/insns/vslide1up_vx.h')
| -rw-r--r-- | riscv/insns/vslide1up_vx.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/insns/vslide1up_vx.h b/riscv/insns/vslide1up_vx.h index 214512a..5154259 100644 --- a/riscv/insns/vslide1up_vx.h +++ b/riscv/insns/vslide1up_vx.h @@ -2,7 +2,7 @@ require((insn.rs2() & (P.VU.vlmul - 1)) == 0); require((insn.rd() & (P.VU.vlmul - 1)) == 0); require(insn.rd() != insn.rs2()); -if (insn.v_vm() == 0) +if (insn.v_vm() == 0 && P.VU.vlmul > 1) require(insn.rd() != 0); VI_LOOP_BASE |