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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-10-22 21:36:05 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-11-11 19:02:34 -0800 |
| commit | f5a68933e509620326d6ff90b449dd074ae915ea (patch) | |
| tree | b02ee0b01dcea477c801883901c23c88db6c226b /riscv/insns/vsadd_vv.h | |
| parent | b15c431738c35417988dd382f3050677efeaa7cc (diff) | |
| download | spike-f5a68933e509620326d6ff90b449dd074ae915ea.zip spike-f5a68933e509620326d6ff90b449dd074ae915ea.tar.gz spike-f5a68933e509620326d6ff90b449dd074ae915ea.tar.bz2 | |
rvv: add reg checking rule for general fomrat
for most instruction which are in
single, single, single/scalar/immediate format
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/insns/vsadd_vv.h')
| -rw-r--r-- | riscv/insns/vsadd_vv.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/insns/vsadd_vv.h b/riscv/insns/vsadd_vv.h index 2152bab..ce0ef40 100644 --- a/riscv/insns/vsadd_vv.h +++ b/riscv/insns/vsadd_vv.h @@ -1,4 +1,5 @@ // vsadd.vv vd, vs2, vs1 +VI_CHECK_SSS(true); VI_LOOP_BASE bool sat = false; switch(sew) { |