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author | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-08-10 22:55:07 +0800 |
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committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-08-10 23:05:58 +0800 |
commit | ce34edb0eecec520d6d2cfec5bda57ca90a69f14 (patch) | |
tree | f5f5da62f53bced28e38349a1b41983bb916dcfa /riscv/insns/vrem_vv.h | |
parent | 2aaa89c0cf8fe0f45d284c0847f11d175eb82e03 (diff) | |
download | spike-ce34edb0eecec520d6d2cfec5bda57ca90a69f14.zip spike-ce34edb0eecec520d6d2cfec5bda57ca90a69f14.tar.gz spike-ce34edb0eecec520d6d2cfec5bda57ca90a69f14.tar.bz2 |
Add space between if/while/switch and '('
Add space between ')' and '{'
Diffstat (limited to 'riscv/insns/vrem_vv.h')
-rw-r--r-- | riscv/insns/vrem_vv.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/insns/vrem_vv.h b/riscv/insns/vrem_vv.h index 260716a..5c58fa4 100644 --- a/riscv/insns/vrem_vv.h +++ b/riscv/insns/vrem_vv.h @@ -3,7 +3,7 @@ VI_VV_LOOP ({ if (vs1 == 0) vd = vs2; - else if(vs2 == -(((intmax_t)1) << (sew - 1)) && vs1 == -1) + else if (vs2 == -(((intmax_t)1) << (sew - 1)) && vs1 == -1) vd = 0; else { vd = vs2 % vs1; |