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| author | Han-Kuan Chen <hankuan.chen@sifive.com> | 2020-09-16 02:00:46 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-09-15 11:00:46 -0700 |
| commit | 3e7cba464d9ce1a5ca5030b7e689d189874f8c75 (patch) | |
| tree | a1cd0d93db4c35b5ce96e6783d809f24924b125c /riscv/insns/vrem_vv.h | |
| parent | a3376ff9af100f6f58ebdb18864eda6ac68b51af (diff) | |
| download | spike-3e7cba464d9ce1a5ca5030b7e689d189874f8c75.zip spike-3e7cba464d9ce1a5ca5030b7e689d189874f8c75.tar.gz spike-3e7cba464d9ce1a5ca5030b7e689d189874f8c75.tar.bz2 | |
rvv: fix int type is not enough to do shift (#544)
int can only represent 32 bit in lp64 model
when sew is greater than 32, the behavior is undefined
Diffstat (limited to 'riscv/insns/vrem_vv.h')
| -rw-r--r-- | riscv/insns/vrem_vv.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/insns/vrem_vv.h b/riscv/insns/vrem_vv.h index da477f0..260716a 100644 --- a/riscv/insns/vrem_vv.h +++ b/riscv/insns/vrem_vv.h @@ -3,7 +3,7 @@ VI_VV_LOOP ({ if (vs1 == 0) vd = vs2; - else if(vs2 == -(1 << (sew - 1)) && vs1 == -1) + else if(vs2 == -(((intmax_t)1) << (sew - 1)) && vs1 == -1) vd = 0; else { vd = vs2 % vs1; |