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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-10-07 02:27:37 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-11-11 19:02:34 -0800 |
| commit | 1cd989add98a8796bf57902853e911608aa737dd (patch) | |
| tree | 0e5e6ddc16b7bf74ef83ce7e818a72089320e944 /riscv/insns/vnsrl_vx.h | |
| parent | 60e3ed49523c2a1af8b7a115593da42d15515732 (diff) | |
| download | spike-1cd989add98a8796bf57902853e911608aa737dd.zip spike-1cd989add98a8796bf57902853e911608aa737dd.tar.gz spike-1cd989add98a8796bf57902853e911608aa737dd.tar.bz2 | |
rvv: add register using check for wide and narrow insn
include
1. narrow shift
2. narrow clip
3. wide mac
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/insns/vnsrl_vx.h')
| -rw-r--r-- | riscv/insns/vnsrl_vx.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/insns/vnsrl_vx.h b/riscv/insns/vnsrl_vx.h index e149b38..8356a2b 100644 --- a/riscv/insns/vnsrl_vx.h +++ b/riscv/insns/vnsrl_vx.h @@ -2,4 +2,4 @@ VI_VX_LOOP_NSHIFT ({ vd = vs2_u >> (rs1 & (sew * 2 - 1)); -}) +}, false) |