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| author | Andrew Waterman <andrew@sifive.com> | 2022-09-22 18:35:12 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-10-04 15:40:27 -0700 |
| commit | e2139a5d1c11954ede663539c8666e8696474c01 (patch) | |
| tree | c72b29369da9ba366a5b83c09cb183214011bdb5 /riscv/insns/vmvnfr_v.h | |
| parent | d2f34d1e41a7d2884aec4d1d3daa1dbf549d059e (diff) | |
| download | spike-e2139a5d1c11954ede663539c8666e8696474c01.zip spike-e2139a5d1c11954ede663539c8666e8696474c01.tar.gz spike-e2139a5d1c11954ede663539c8666e8696474c01.tar.bz2 | |
Suppress unused-variable warnings in vector instruction definitions
Diffstat (limited to 'riscv/insns/vmvnfr_v.h')
| -rw-r--r-- | riscv/insns/vmvnfr_v.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/riscv/insns/vmvnfr_v.h b/riscv/insns/vmvnfr_v.h index 543ac58..9c52810 100644 --- a/riscv/insns/vmvnfr_v.h +++ b/riscv/insns/vmvnfr_v.h @@ -1,6 +1,5 @@ // vmv<nf>r.v vd, vs2 require_vector(true); -const reg_t baseAddr = RS1; const reg_t vd = insn.rd(); const reg_t vs2 = insn.rs2(); const reg_t len = insn.rs1() + 1; |