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| author | Andrew Waterman <andrew@sifive.com> | 2019-07-19 00:23:32 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-07-19 00:25:46 -0700 |
| commit | ec29540ebe1e98124e3d13b3a73bb9d262c4858b (patch) | |
| tree | b268184ac3355b6b0220c5a2b9bf8456e40d7853 /riscv/insns/vmv_x_s.h | |
| parent | 3f200ac315c53d8caae1e454c19b655e6b35048b (diff) | |
| download | spike-ec29540ebe1e98124e3d13b3a73bb9d262c4858b.zip spike-ec29540ebe1e98124e3d13b3a73bb9d262c4858b.tar.gz spike-ec29540ebe1e98124e3d13b3a73bb9d262c4858b.tar.bz2 | |
vext.x.v -> vmv.x.s; unary operation encoding changes
https://github.com/riscv/riscv-v-spec/commit/83fc27897b7b1fbc68e2e9e94f2ee05766315bac
https://github.com/riscv/riscv-v-spec/commit/fb40ef10f068827f3f0a926a83dd38ebcd470085
Diffstat (limited to 'riscv/insns/vmv_x_s.h')
| -rw-r--r-- | riscv/insns/vmv_x_s.h | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/riscv/insns/vmv_x_s.h b/riscv/insns/vmv_x_s.h new file mode 100644 index 0000000..f22c2dd --- /dev/null +++ b/riscv/insns/vmv_x_s.h @@ -0,0 +1,25 @@ +// vext_x_v: rd = vs2[0] +require(insn.v_vm() == 1); +uint64_t xmask = UINT64_MAX >> (64 - P.get_max_xlen()); +VI_LOOP_BASE +VI_LOOP_END_NO_TAIL_ZERO +switch(sew) { +case e8: + WRITE_RD(P.VU.elt<uint8_t>(rs2_num, 0)); + break; +case e16: + WRITE_RD(P.VU.elt<uint16_t>(rs2_num, 0)); + break; +case e32: + if (P.get_max_xlen() == 32) + WRITE_RD(P.VU.elt<int32_t>(rs2_num, 0)); + else + WRITE_RD(P.VU.elt<uint32_t>(rs2_num, 0)); + break; +case e64: + if (P.get_max_xlen() <= sew) + WRITE_RD(P.VU.elt<uint64_t>(rs2_num, 0) & xmask); + else + WRITE_RD(P.VU.elt<uint64_t>(rs2_num, 0)); + break; +} |