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| author | Scott Johnson <scott.johnson@arilinc.com> | 2021-09-29 12:44:24 -0700 |
|---|---|---|
| committer | Scott Johnson <scott.johnson@arilinc.com> | 2021-09-29 14:31:52 -0700 |
| commit | 72a6f9fac8f3c058d72af54a8554ee6fab2627ec (patch) | |
| tree | c05152e49d35fadc9337c1ac6708da1b78401190 /riscv/insns/vmsif_m.h | |
| parent | 347ff31125bee0fadd8e02bbe7a13c672dcf74a5 (diff) | |
| download | spike-72a6f9fac8f3c058d72af54a8554ee6fab2627ec.zip spike-72a6f9fac8f3c058d72af54a8554ee6fab2627ec.tar.gz spike-72a6f9fac8f3c058d72af54a8554ee6fab2627ec.tar.bz2 | |
Convert vstart to csr_t
Adds commit log events for vstart to many vector instructions.
Diffstat (limited to 'riscv/insns/vmsif_m.h')
| -rw-r--r-- | riscv/insns/vmsif_m.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/insns/vmsif_m.h b/riscv/insns/vmsif_m.h index a16ef68..8867646 100644 --- a/riscv/insns/vmsif_m.h +++ b/riscv/insns/vmsif_m.h @@ -1,7 +1,7 @@ // vmsif.m rd, vs2, vm require(P.VU.vsew >= e8 && P.VU.vsew <= e64); require_vector(true); -require(P.VU.vstart == 0); +require(P.VU.vstart->read() == 0); require_vm; require(insn.rd() != insn.rs2()); @@ -10,7 +10,7 @@ reg_t rd_num = insn.rd(); reg_t rs2_num = insn.rs2(); bool has_one = false; -for (reg_t i = P.VU.vstart ; i < vl; ++i) { +for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { const int midx = i / 64; const int mpos = i % 64; const uint64_t mmask = UINT64_C(1) << mpos; \ |