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authorChih-Min Chao <chihmin.chao@sifive.com>2020-08-03 01:25:53 -0700
committerChih-Min Chao <chihmin.chao@sifive.com>2020-08-03 21:53:16 -0700
commit6e4977abdbe16dc7923a709cf3b3defb871c9061 (patch)
tree579ac656ad7c3aceef1265004ef9e094c9937074 /riscv/insns/vmsif_m.h
parent959700ec11d5c5e8417533e6cddfada1a83c4770 (diff)
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rvv: add 'vstartalu" option to --varch arugment
except for load/store instructions 0 : all instruction can't have non-zero vstart not 0 : all instruction can have non-zero vstart if it is not required vstart must be zero in spec the default value is 1 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/insns/vmsif_m.h')
-rw-r--r--riscv/insns/vmsif_m.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/insns/vmsif_m.h b/riscv/insns/vmsif_m.h
index 6e941eb..a16ef68 100644
--- a/riscv/insns/vmsif_m.h
+++ b/riscv/insns/vmsif_m.h
@@ -1,6 +1,6 @@
// vmsif.m rd, vs2, vm
require(P.VU.vsew >= e8 && P.VU.vsew <= e64);
-require_vector;
+require_vector(true);
require(P.VU.vstart == 0);
require_vm;
require(insn.rd() != insn.rs2());