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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-12-11 00:26:01 -0800 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-12-12 00:29:24 -0800 |
| commit | 7be9d34b63683b44558b78f2cb99d0b55ae98911 (patch) | |
| tree | dbff9f6d9104672458c688244de130dc6c403a20 /riscv/insns/vfncvt_x_f_w.h | |
| parent | c529835050826628bd3c76d93d06e7a1b41e6c29 (diff) | |
| download | spike-7be9d34b63683b44558b78f2cb99d0b55ae98911.zip spike-7be9d34b63683b44558b78f2cb99d0b55ae98911.tar.gz spike-7be9d34b63683b44558b78f2cb99d0b55ae98911.tar.bz2 | |
rvv: fix vfwcvt/vfncvt for f32 -> f64 and f64 -> f32
1. fix disam
2. refine checking rule and move them out of loop
3. add missing exception keeping for each element
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/insns/vfncvt_x_f_w.h')
| -rw-r--r-- | riscv/insns/vfncvt_x_f_w.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/riscv/insns/vfncvt_x_f_w.h b/riscv/insns/vfncvt_x_f_w.h index 8985f1b..baf27fa 100644 --- a/riscv/insns/vfncvt_x_f_w.h +++ b/riscv/insns/vfncvt_x_f_w.h @@ -1,6 +1,7 @@ // vfncvt.x.f.v vd, vs2, vm +VI_CHECK_SDS(false); VI_VFP_LOOP_BASE - VI_CHECK_SD; auto vs2 = P.VU.elt<float64_t>(rs2_num, i); P.VU.elt<int32_t>(rd_num, i) = f64_to_i32(vs2, STATE.frm, true); + set_fp_exceptions; VI_VFP_LOOP_END |