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authorAndrew Waterman <andrew@sifive.com>2022-10-17 13:51:59 -0700
committerAndrew Waterman <andrew@sifive.com>2022-10-17 13:51:59 -0700
commit68aeeb5500521ff52c216862f9a653b64191f3ad (patch)
tree407230ff48f79f177a792451598d9b2b6e3d34a0 /riscv/insns/vdiv_vx.h
parent191634d2854dfed448fc323195f9b65c305e2d77 (diff)
parent03be4ae6c7b8e9865083b61427ff9724c7706fcf (diff)
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Merge branch 'master' into plic_uart_v1plic_uart_v1
Diffstat (limited to 'riscv/insns/vdiv_vx.h')
-rw-r--r--riscv/insns/vdiv_vx.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/insns/vdiv_vx.h b/riscv/insns/vdiv_vx.h
index 4052952..2b93eac 100644
--- a/riscv/insns/vdiv_vx.h
+++ b/riscv/insns/vdiv_vx.h
@@ -1,9 +1,9 @@
// vdiv.vx vd, vs2, rs1
VI_VX_LOOP
({
- if(rs1 == 0)
+ if (rs1 == 0)
vd = -1;
- else if(vs2 == (INT64_MIN >> (64 - sew)) && rs1 == -1)
+ else if (vs2 == (INT64_MIN >> (64 - sew)) && rs1 == -1)
vd = vs2;
else
vd = vs2 / rs1;