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| author | Anup Patel <anup.patel@wdc.com> | 2020-06-13 15:38:21 +0530 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2020-07-09 23:04:07 +0530 |
| commit | 9af85e39a550ba031e4fe9c1913e275959a9927b (patch) | |
| tree | 40e434e8473c0ef517461a0e2d5add4887a27110 /riscv/insns/sret.h | |
| parent | b6038de3fcd71703732995bb90bd7d411d330890 (diff) | |
| download | spike-9af85e39a550ba031e4fe9c1913e275959a9927b.zip spike-9af85e39a550ba031e4fe9c1913e275959a9927b.tar.gz spike-9af85e39a550ba031e4fe9c1913e275959a9927b.tar.bz2 | |
Implement hypervisor CSRs read/write
We add newly defined hypervisor CSRs and allow M/HS-mode to access
these CSRs. The MRET, SRET, ECALL and WFI instructions have also
been updated so that virt-to-novirt switch and exception cause is
based on HART virtualization state.
Subsequent patches will implement two-stage page tables, HFENCE
instructions and HSV/HLV instructions.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Diffstat (limited to 'riscv/insns/sret.h')
| -rw-r--r-- | riscv/insns/sret.h | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/riscv/insns/sret.h b/riscv/insns/sret.h index be837a3..bc063e6 100644 --- a/riscv/insns/sret.h +++ b/riscv/insns/sret.h @@ -1,10 +1,17 @@ require_extension('S'); require_privilege(get_field(STATE.mstatus, MSTATUS_TSR) ? PRV_M : PRV_S); -set_pc_and_serialize(p->get_state()->sepc); +if (STATE.v && get_field(STATE.hstatus, HSTATUS_VTSR)) + require_novirt(); +reg_t next_pc = (STATE.v) ? p->get_state()->vsepc : p->get_state()->sepc; +set_pc_and_serialize(next_pc); reg_t s = STATE.mstatus; reg_t prev_prv = get_field(s, MSTATUS_SPP); s = set_field(s, MSTATUS_SIE, get_field(s, MSTATUS_SPIE)); s = set_field(s, MSTATUS_SPIE, 1); s = set_field(s, MSTATUS_SPP, PRV_U); -p->set_privilege(prev_prv); p->set_csr(CSR_MSTATUS, s); +p->set_privilege(prev_prv); +if (!STATE.v) { + reg_t prev_virt = get_field(STATE.hstatus, HSTATUS_SPV); + p->set_virt(prev_virt); +} |