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author | Andrew Waterman <andrew@sifive.com> | 2020-09-21 17:53:35 -0700 |
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committer | Andrew Waterman <andrew@sifive.com> | 2020-09-21 17:53:35 -0700 |
commit | ac46e18f82fd2c040680633e089860998baa5a5d (patch) | |
tree | c199bbf7284de55b52eaa8b2c66e774bce73f219 /riscv/insns/sfence_vma.h | |
parent | fbb5a7620ffd2d6f7583148881e2c9fc501a4614 (diff) | |
download | spike-ac46e18f82fd2c040680633e089860998baa5a5d.zip spike-ac46e18f82fd2c040680633e089860998baa5a5d.tar.gz spike-ac46e18f82fd2c040680633e089860998baa5a5d.tar.bz2 |
Raise virtual-instruction traps correctly for WFI/SRET/SFENCE
Diffstat (limited to 'riscv/insns/sfence_vma.h')
-rw-r--r-- | riscv/insns/sfence_vma.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/riscv/insns/sfence_vma.h b/riscv/insns/sfence_vma.h index 3d42b70..aca14d0 100644 --- a/riscv/insns/sfence_vma.h +++ b/riscv/insns/sfence_vma.h @@ -1,3 +1,5 @@ require_extension('S'); +if (STATE.v && (STATE.prv == PRV_U || get_field(STATE.hstatus, HSTATUS_VTVM))) + require_novirt(); require_privilege(get_field(STATE.mstatus, MSTATUS_TVM) ? PRV_M : PRV_S); MMU.flush_tlb(); |