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author | Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2011-04-23 21:31:50 -0700 |
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committer | Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2011-04-23 21:31:50 -0700 |
commit | c0cd05e70b496598033134acd5e038502d3763f0 (patch) | |
tree | 102f1ca76bba8709a18df902f2a67726145add8d /riscv/insns/remw.h | |
parent | c6b549289aa0f6d975307ebdddbbd6b8b0a31e7e (diff) | |
download | spike-c0cd05e70b496598033134acd5e038502d3763f0.zip spike-c0cd05e70b496598033134acd5e038502d3763f0.tar.gz spike-c0cd05e70b496598033134acd5e038502d3763f0.tar.bz2 |
[sim] fixed divw/remw crashing simulator
Diffstat (limited to 'riscv/insns/remw.h')
-rw-r--r-- | riscv/insns/remw.h | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/riscv/insns/remw.h b/riscv/insns/remw.h index c338516..93c3858 100644 --- a/riscv/insns/remw.h +++ b/riscv/insns/remw.h @@ -1,9 +1,7 @@ require_xpr64; -// INT64_MIN/-1 corner case shouldn't occur in correct code, since -// INT64_MIN is not a proper 32-bit signed value if(RS2 == 0) RD = RS1; -else if(sreg_t(RS1) == INT64_MIN && sreg_t(RS2) == -1) +else if(int32_t(RS1) == INT32_MIN && int32_t(RS2) == -1) RD = 0; else RD = sext32(int32_t(RS1) % int32_t(RS2)); |