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| author | Andrew Waterman <andrew@sifive.com> | 2017-09-24 20:34:04 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-09-28 15:56:47 -0700 |
| commit | 85c40db208db3e26f507dc6a74a5dc540b504b5c (patch) | |
| tree | 88ddd7440be666a4305a55e4ca1130ae7636a4f6 /riscv/insns/fsw.h | |
| parent | bd85811c35ea38180d27440507fc222d585ef780 (diff) | |
| download | spike-85c40db208db3e26f507dc6a74a5dc540b504b5c.zip spike-85c40db208db3e26f507dc6a74a5dc540b504b5c.tar.gz spike-85c40db208db3e26f507dc6a74a5dc540b504b5c.tar.bz2 | |
Implement Q extension
Diffstat (limited to 'riscv/insns/fsw.h')
| -rw-r--r-- | riscv/insns/fsw.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/insns/fsw.h b/riscv/insns/fsw.h index 42fc683..8af5184 100644 --- a/riscv/insns/fsw.h +++ b/riscv/insns/fsw.h @@ -1,3 +1,3 @@ require_extension('F'); require_fp; -MMU.store_uint32(RS1 + insn.s_imm(), FRS2.v); +MMU.store_uint32(RS1 + insn.s_imm(), FRS2.v[0]); |