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| author | Andrew Waterman <andrew@sifive.com> | 2017-10-19 12:18:23 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-10-19 12:18:23 -0700 |
| commit | 27ffc270f4e08862606e3532a87556e2f16fa87b (patch) | |
| tree | 9ec4bd52bef3ebd3ac138c514a69d03922a1d478 /riscv/insns/fmin_s.h | |
| parent | a91d9f7d89abd6cda6fafb7b5e7cacf4b3590c29 (diff) | |
| download | spike-27ffc270f4e08862606e3532a87556e2f16fa87b.zip spike-27ffc270f4e08862606e3532a87556e2f16fa87b.tar.gz spike-27ffc270f4e08862606e3532a87556e2f16fa87b.tar.bz2 | |
Fix implementation of FMIN/FMAX NaN case
If rd=rs1 or rd=rs2, the NaN check examined the wrong value.
Diffstat (limited to 'riscv/insns/fmin_s.h')
| -rw-r--r-- | riscv/insns/fmin_s.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/riscv/insns/fmin_s.h b/riscv/insns/fmin_s.h index 8099003..19e1193 100644 --- a/riscv/insns/fmin_s.h +++ b/riscv/insns/fmin_s.h @@ -2,7 +2,8 @@ require_extension('F'); require_fp; bool less = f32_lt_quiet(f32(FRS1), f32(FRS2)) || (f32_eq(f32(FRS1), f32(FRS2)) && (f32(FRS1).v & F32_SIGN)); -WRITE_FRD(less || isNaNF32UI(f32(FRS2).v) ? FRS1 : FRS2); if (isNaNF32UI(f32(FRS1).v) && isNaNF32UI(f32(FRS2).v)) WRITE_FRD(f32(defaultNaNF32UI)); +else + WRITE_FRD(less || isNaNF32UI(f32(FRS2).v) ? FRS1 : FRS2); set_fp_exceptions; |