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| author | Andrew Waterman <andrew@sifive.com> | 2018-02-22 15:19:26 -0800 |
|---|---|---|
| committer | Andrew Waterman <aswaterman@gmail.com> | 2018-03-03 13:47:54 -0600 |
| commit | 4299874ad4b07ef457776513a64e5b2397a6a75e (patch) | |
| tree | 66e952f79375892d256a0f9c0d985f2f109da496 /riscv/insns/csrrwi.h | |
| parent | e91d3a441e9391054eecd371922649b7f540cc52 (diff) | |
| download | spike-4299874ad4b07ef457776513a64e5b2397a6a75e.zip spike-4299874ad4b07ef457776513a64e5b2397a6a75e.tar.gz spike-4299874ad4b07ef457776513a64e5b2397a6a75e.tar.bz2 | |
Implement clearing-misa.C-while-PC-is-misaligned proposal
See https://github.com/riscv/riscv-isa-manual/pull/139
Not adopted yet, but I'm putting the implementation here for reference.
Diffstat (limited to 'riscv/insns/csrrwi.h')
| -rw-r--r-- | riscv/insns/csrrwi.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/insns/csrrwi.h b/riscv/insns/csrrwi.h index cf0710f..decadf4 100644 --- a/riscv/insns/csrrwi.h +++ b/riscv/insns/csrrwi.h @@ -2,3 +2,4 @@ int csr = validate_csr(insn.csr(), true); reg_t old = p->get_csr(csr); p->set_csr(csr, insn.rs1()); WRITE_RD(sext_xlen(old)); +serialize(); |