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author | Clifford Wolf <clifford@clifford.at> | 2019-08-11 14:48:11 +0200 |
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committer | Andrew Waterman <andrew@sifive.com> | 2020-10-22 17:00:11 -0700 |
commit | 70d7081acb5be54ea7fa4c3f9ef9a6134a43519e (patch) | |
tree | 6bf1c33283d13b4b197047f225d45cd253ceaccf /riscv/insns/clmulrw.h | |
parent | f1c24eff543e6f41980993f41ae1ab5ab80a7340 (diff) | |
download | spike-70d7081acb5be54ea7fa4c3f9ef9a6134a43519e.zip spike-70d7081acb5be54ea7fa4c3f9ef9a6134a43519e.tar.gz spike-70d7081acb5be54ea7fa4c3f9ef9a6134a43519e.tar.bz2 |
[riscv-bitmanip] Add bitmanip instructions
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'riscv/insns/clmulrw.h')
-rw-r--r-- | riscv/insns/clmulrw.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/riscv/insns/clmulrw.h b/riscv/insns/clmulrw.h new file mode 100644 index 0000000..6fc9008 --- /dev/null +++ b/riscv/insns/clmulrw.h @@ -0,0 +1,6 @@ +require_extension('B'); +reg_t a = zext32(RS1), b = zext32(RS2), x = 0; +for (int i = 0; i < 32; i++) + if ((b >> i) & 1) + x ^= a >> (31-i); +WRITE_RD(sext32(x)); |