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| author | Andrew Waterman <andrew@sifive.com> | 2016-11-10 13:40:37 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2016-11-10 13:40:37 -0800 |
| commit | bf8d2b71bb76b03b9a4db36fe6928c29a41a43e7 (patch) | |
| tree | 7511583efc9104a4309a9238ea6ed0aa60c19cd7 /riscv/insns/amoand_w.h | |
| parent | ecff67fb34d50cc80822301f4de986be96da971c (diff) | |
| download | spike-bf8d2b71bb76b03b9a4db36fe6928c29a41a43e7.zip spike-bf8d2b71bb76b03b9a4db36fe6928c29a41a43e7.tar.gz spike-bf8d2b71bb76b03b9a4db36fe6928c29a41a43e7.tar.bz2 | |
AMOs should always return store faults, not load faults
This commit also factors out the common AMO code into mmu_t.
Diffstat (limited to 'riscv/insns/amoand_w.h')
| -rw-r--r-- | riscv/insns/amoand_w.h | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/riscv/insns/amoand_w.h b/riscv/insns/amoand_w.h index 7db2160..f7e1ba7 100644 --- a/riscv/insns/amoand_w.h +++ b/riscv/insns/amoand_w.h @@ -1,4 +1,2 @@ require_extension('A'); -reg_t v = MMU.load_int32(RS1); -MMU.store_uint32(RS1, RS2 & v); -WRITE_RD(v); +WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](uint32_t lhs) { return lhs & RS2; }))); |