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| author | Andrew Waterman <andrew@sifive.com> | 2022-01-06 17:19:11 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-01-06 17:21:06 -0800 |
| commit | fc572daaef35fdc081466e6a67413b1f3b4d6a3e (patch) | |
| tree | 1b13e962055a28f0d3044720f2f6e2b05c3addfc /riscv/insn_template.cc | |
| parent | 2fbc6cde0b6b0e7d4ef77ae092c4ae286a77e2bf (diff) | |
| download | spike-fc572daaef35fdc081466e6a67413b1f3b4d6a3e.zip spike-fc572daaef35fdc081466e6a67413b1f3b4d6a3e.tar.gz spike-fc572daaef35fdc081466e6a67413b1f3b4d6a3e.tar.bz2 | |
Support RV32E/RV64E base ISAs
Diffstat (limited to 'riscv/insn_template.cc')
| -rw-r--r-- | riscv/insn_template.cc | 27 |
1 files changed, 25 insertions, 2 deletions
diff --git a/riscv/insn_template.cc b/riscv/insn_template.cc index b3dd330..e6a2f52 100644 --- a/riscv/insn_template.cc +++ b/riscv/insn_template.cc @@ -3,7 +3,7 @@ #include "insn_template.h" #include "insn_macros.h" -reg_t rv32_NAME(processor_t* p, insn_t insn, reg_t pc) +reg_t rv32i_NAME(processor_t* p, insn_t insn, reg_t pc) { #define xlen 32 reg_t npc = sext_xlen(pc + insn_length(OPCODE)); @@ -13,7 +13,30 @@ reg_t rv32_NAME(processor_t* p, insn_t insn, reg_t pc) return npc; } -reg_t rv64_NAME(processor_t* p, insn_t insn, reg_t pc) +reg_t rv64i_NAME(processor_t* p, insn_t insn, reg_t pc) +{ + #define xlen 64 + reg_t npc = sext_xlen(pc + insn_length(OPCODE)); + #include "insns/NAME.h" + trace_opcode(p, OPCODE, insn); + #undef xlen + return npc; +} + +#undef CHECK_REG +#define CHECK_REG(reg) require((reg) < 16) + +reg_t rv32e_NAME(processor_t* p, insn_t insn, reg_t pc) +{ + #define xlen 32 + reg_t npc = sext_xlen(pc + insn_length(OPCODE)); + #include "insns/NAME.h" + trace_opcode(p, OPCODE, insn); + #undef xlen + return npc; +} + +reg_t rv64e_NAME(processor_t* p, insn_t insn, reg_t pc) { #define xlen 64 reg_t npc = sext_xlen(pc + insn_length(OPCODE)); |