Generate instruction decoder dynamically

This will make it easier for accelerators to add instructions.

1 files changed, 25 insertions, 0 deletions

diff --git a/riscv/insn_template.cc b/riscv/insn_template.cc
new file mode 100644
index 0000000..3aca669
--- /dev/null
+++ b/riscv/insn_template.cc
@@ -0,0 +1,25 @@
+// See LICENSE for license details.
+
+#include "processor.h"
+#include "config.h"
+#include "sim.h"
+#include "softfloat.h"
+#include "platform.h" // softfloat isNaNF32UI, etc.
+#include "internals.h" // ditto
+#include <assert.h>
+
+reg_t processor_t::rv32_NAME(insn_t insn, reg_t pc)
+{
+  int xprlen = 32;
+  reg_t npc = sext_xprlen(pc + insn_length(OPCODE));
+  #include "insns/NAME.h"
+  return npc;
+}
+
+reg_t processor_t::rv64_NAME(insn_t insn, reg_t pc)
+{
+  int xprlen = 64;
+  reg_t npc = sext_xprlen(pc + insn_length(OPCODE));
+  #include "insns/NAME.h"
+  return npc;
+}