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| author | Tim Newsome <tim@sifive.com> | 2016-12-15 21:12:34 -0800 |
|---|---|---|
| committer | Andrew Waterman <aswaterman@gmail.com> | 2016-12-15 21:12:34 -0800 |
| commit | 7e31f495358df52e49b9a5fec7ce273d706b1300 (patch) | |
| tree | 986e275848b4393adf33590135dc8a8a7e55e5cc /riscv/execute.cc | |
| parent | 481afc249eeb63de3f47700af505343a53ffd1b1 (diff) | |
| download | spike-7e31f495358df52e49b9a5fec7ce273d706b1300.zip spike-7e31f495358df52e49b9a5fec7ce273d706b1300.tar.gz spike-7e31f495358df52e49b9a5fec7ce273d706b1300.tar.bz2 | |
Fix single stepping over faulting instructions. (#80)
Diffstat (limited to 'riscv/execute.cc')
| -rw-r--r-- | riscv/execute.cc | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/riscv/execute.cc b/riscv/execute.cc index 36e7896..eb9fe4b 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -190,6 +190,11 @@ miss: { take_trap(t, pc); n = instret; + + if (unlikely(state.single_step == state.STEP_STEPPED)) { + state.single_step = state.STEP_NONE; + enter_debug_mode(DCSR_CAUSE_STEP); + } } catch (trigger_matched_t& t) { |