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| author | Andrew Waterman <andrew@sifive.com> | 2019-07-12 11:55:01 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-07-22 02:11:03 -0700 |
| commit | 4367fd1b4be8bbe7f45d9a439531aff183c6f18a (patch) | |
| tree | 4bc7808b58ab2ec67f5f9343f7a7a4305570b194 /riscv/execute.cc | |
| parent | a1655f21604e773f01499ebf3c44e78a23113a7b (diff) | |
| download | spike-4367fd1b4be8bbe7f45d9a439531aff183c6f18a.zip spike-4367fd1b4be8bbe7f45d9a439531aff183c6f18a.tar.gz spike-4367fd1b4be8bbe7f45d9a439531aff183c6f18a.tar.bz2 | |
Add debug_mode state bit, rather than overloading dcsr.cause
In the previous scheme, debug-mode software could exit debug mode by
zeroing the dcsr.cause field. While benign, that behavior is out of
spec.
Diffstat (limited to 'riscv/execute.cc')
| -rw-r--r-- | riscv/execute.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/riscv/execute.cc b/riscv/execute.cc index 6be18aa..ac9294d 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -85,7 +85,7 @@ static reg_t execute_insn(processor_t* p, reg_t pc, insn_fetch_t fetch) bool processor_t::slow_path() { - return debug || state.single_step != state.STEP_NONE || state.dcsr.cause; + return debug || state.single_step != state.STEP_NONE || state.debug_mode; } extern const char* xpr_name[NXPR]; @@ -95,7 +95,7 @@ extern const char* vr_name[NVPR]; // fetch/decode/execute loop void processor_t::step(size_t n) { - if (state.dcsr.cause == DCSR_CAUSE_NONE) { + if (!state.debug_mode) { if (halt_request) { enter_debug_mode(DCSR_CAUSE_DEBUGINT); } // !!!The halt bit in DCSR is deprecated. @@ -134,7 +134,7 @@ void processor_t::step(size_t n) { if (unlikely(!state.serialized && state.single_step == state.STEP_STEPPED)) { state.single_step = state.STEP_NONE; - if (state.dcsr.cause == DCSR_CAUSE_NONE) { + if (!state.debug_mode) { enter_debug_mode(DCSR_CAUSE_STEP); // enter_debug_mode changed state.pc, so we can't just continue. break; |