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author | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-08-25 21:27:10 -0700 |
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committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-08-25 21:27:10 -0700 |
commit | bc49f60710d95c577079a9d8f0c7ccc8c5f2c98c (patch) | |
tree | ec1a980fd8438fdad782606af1494f0d3520b18f /riscv/execute.cc | |
parent | c8149cb261631aadfe6d984cb9b40b88bfb31408 (diff) | |
download | spike-bc49f60710d95c577079a9d8f0c7ccc8c5f2c98c.zip spike-bc49f60710d95c577079a9d8f0c7ccc8c5f2c98c.tar.gz spike-bc49f60710d95c577079a9d8f0c7ccc8c5f2c98c.tar.bz2 |
partially update spike to newer debug spec
Diffstat (limited to 'riscv/execute.cc')
-rw-r--r-- | riscv/execute.cc | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/riscv/execute.cc b/riscv/execute.cc index 0cb70e5..7b42262 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -169,13 +169,17 @@ miss: delete mmu->matched_trigger; mmu->matched_trigger = NULL; } - assert(state.mcontrol[t.index].action != ACTION_NONE); switch (state.mcontrol[t.index].action) { case ACTION_DEBUG_MODE: enter_debug_mode(DCSR_CAUSE_HWBP); break; + case ACTION_DEBUG_EXCEPTION: { + mem_trap_t trap(CAUSE_BREAKPOINT, t.address); + take_trap(trap, pc); + break; + } default: - assert(0); + abort(); } } |