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| author | Tim Newsome <tim@sifive.com> | 2016-05-05 11:21:07 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2016-05-23 12:12:12 -0700 |
| commit | a950cdebb61e2e86b01becff288e0240c77aa1e5 (patch) | |
| tree | a433ea9aa2f041029db050dc38b3cd55fa10fca5 /riscv/execute.cc | |
| parent | dd233bc49946aa059b6ea9494b870d20076ce1b8 (diff) | |
| download | spike-a950cdebb61e2e86b01becff288e0240c77aa1e5.zip spike-a950cdebb61e2e86b01becff288e0240c77aa1e5.tar.gz spike-a950cdebb61e2e86b01becff288e0240c77aa1e5.tar.bz2 | |
Fix reading CSRs.
Diffstat (limited to 'riscv/execute.cc')
| -rw-r--r-- | riscv/execute.cc | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/riscv/execute.cc b/riscv/execute.cc index 8f7b85f..03588f3 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -66,10 +66,6 @@ void processor_t::step(size_t n) n = std::min(n, (size_t) 11); } - if (debug) { - fprintf(stderr, "step(%ld)\n", n); - } - while (n > 0) { size_t instret = 0; reg_t pc = state.pc; |