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| author | Andrew Waterman <andrew@sifive.com> | 2018-04-30 15:06:52 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-04-30 15:06:52 -0700 |
| commit | 3d016e2765f9ad5f34e471e345004c6e16438e3c (patch) | |
| tree | c9c03645fbd87502e8d18d7947518d83ea33b491 /riscv/execute.cc | |
| parent | c0172e96bc2e83c990a22342ce7e99ba73142c47 (diff) | |
| download | spike-3d016e2765f9ad5f34e471e345004c6e16438e3c.zip spike-3d016e2765f9ad5f34e471e345004c6e16438e3c.tar.gz spike-3d016e2765f9ad5f34e471e345004c6e16438e3c.tar.bz2 | |
Only break out of the simulator loop on WFI, not on CSR writes
Breaking out of the loop on WFI was intended to let other threads run
when the current thread has no work to do. There's no advantage to doing
so on CSR writes, and the unintentional change in thread interleaving
broke some test programs that relied on short timer periods.
Diffstat (limited to 'riscv/execute.cc')
| -rw-r--r-- | riscv/execute.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/riscv/execute.cc b/riscv/execute.cc index 9d1fb87..d7e586d 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -109,7 +109,8 @@ void processor_t::step(size_t n) if (unlikely(invalid_pc(pc))) { \ switch (pc) { \ case PC_SERIALIZE_BEFORE: state.serialized = true; break; \ - case PC_SERIALIZE_AFTER: n = ++instret; break; \ + case PC_SERIALIZE_AFTER: ++instret; break; \ + case PC_SERIALIZE_WFI: n = ++instret; break; \ default: abort(); \ } \ pc = state.pc; \ |